mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2025-04-23 13:04:50 +00:00
extending the register struct
the manual is unordered at times, there is probably still something missing reverted wrong SECURITY_CFG* naming
This commit is contained in:
Resaec
parent
9337162f99
commit
4f5ed74e43
4 changed files with 178 additions and 44 deletions
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@ -86,9 +86,9 @@ void bootup_misc_mmio(void) {
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mc_register->MTS_CARVEOUT_REG_CTRL_0 = 1;
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/* disable security carveout - SECURITY_CFG0_0, CFG1_0, CFG3_0 */
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mc_register->SECURITY_BOM = 0;
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mc_register->SECURITY_SIZE_MB = 0;
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mc_register->SECURITY_BOM_HI = 3;
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mc_register->SECURITY_CFG0_0 = 0;
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mc_register->SECURITY_CFG1_0 = 0;
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mc_register->SECURITY_CFG3_0 = 3;
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configure_default_carveouts();
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@ -39,73 +39,207 @@ typedef struct {
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/* 18.11.1 MC Registers */
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typedef struct {
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uint32_t _0x0[4];
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uint32_t SMMU_CONFIG_0;
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uint32_t INTSTATUS_0;
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uint32_t INTMASK_0;
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uint32_t ERR_STATUS_0;
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uint32_t ERR_ADR_0;
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uint32_t SMMU_CONFIG_0; /* 0x10 */
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uint32_t SMMU_TLB_CONFIG_0; /* Controls usage of the TLB */
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uint32_t SMMU_PTC_CONFIG_0; /* Controls usage of the PTC */
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uint32_t SMMU_PTB_ASID_0;
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uint32_t SMMU_PTB_DATA_0;
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uint32_t _0x24[3];
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uint32_t SMMU_TLB_FLUSH_0;
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uint32_t SMMU_PTB_DATA_0; /* 0x20 */
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uint32_t _0x24[3]; /* undefined */
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uint32_t SMMU_TLB_FLUSH_0; /* 0x30 */
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uint32_t SMMU_PTC_FLUSH_0;
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uint32_t _0x38;
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uint32_t _0x3C;
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uint32_t _0x40[12];
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uint32_t _0x38; /* unknown */
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uint32_t _0x3C; /* unknown */
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uint32_t _0x40[4]; /* undefined */
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uint32_t EMEM_CFG_0; /* 0x50 */
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uint32_t EMEM_ADR_CFG_0;
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uint32_t EMEM_ADR_CFG_DEV0_0;
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uint32_t EMEM_ADR_CFG_DEV1_0;
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uint32_t EMEM_ADR_CFG_CHANNEL_MASK_0; /* 0x60 */
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uint32_t EMEM_ADR_CFG_BANK_MASK_0_0;
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uint32_t EMEM_ADR_CFG_BANK_MASK_1_0;
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uint32_t EMEM_ADR_CFG_BANK_MASK_2_0;
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/* SECURITY_BOM is the base of the secured region, limited to MB granularity.
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This must point to a region of the physical address map allocated to EMEM for it to be effective; the MC cannot secure address space it does not own. (In other words, this is an absolute address, not an offset.)
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Above is the list of clients with the TrustZone-security access. [18.11.1.20]
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Note that AXICIF clients will adhere to the standard AXI protocol "aprot[1]==0" indication for secure requests. */
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uint32_t SECURITY_BOM; /* MC_SECURITY_CFG0_0 */
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uint32_t SECURITY_SIZE_MB; /* MC_SECURITY_CFG1_0 -- SECURITY_SIZE_MB is the size, in megabytes, of the secured region. If set to 0, the security check in MC is disabled */
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uint32_t _0x78[26];
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uint32_t EMEM_ARB_RING1_THROTTLE_0;
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Note that AXICIF clients will adhere to the standard AXI protocol "aprot[1]==0" indication for secure requests.
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0x70
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*/
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uint32_t SECURITY_CFG0_0;
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uint32_t SECURITY_CFG1_0; /* SECURITY_SIZE_MB is the size, in megabytes, of the secured region. If set to 0, the security check in MC is disabled */
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uint32_t _0x78[6]; /* undefined */
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uint32_t EMEM_ARB_CFG_0; /* 0x90 */
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uint32_t EMEM_ARB_OUTSTANDING_REQ_0;
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uint32_t EMEM_ARB_TIMING_RCD_0;
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uint32_t EMEM_ARB_TIMING_RP_0;
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uint32_t EMEM_ARB_TIMING_RC_0; /* 0xA0 */
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uint32_t EMEM_ARB_TIMING_RAS_0;
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uint32_t EMEM_ARB_TIMING_FAW_0;
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uint32_t EMEM_ARB_TIMING_RRD_0;
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uint32_t EMEM_ARB_TIMING_RAP2PRE_0; /* 0xB0 */
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uint32_t EMEM_ARB_TIMING_WAP2PRE_0;
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uint32_t EMEM_ARB_TIMING_R2R_0;
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uint32_t EMEM_ARB_TIMING_W2W_0;
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uint32_t EMEM_ARB_TIMING_R2W_0; /* 0xC0 */
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uint32_t EMEM_ARB_TIMING_W2R_0;
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uint32_t EMEM_ARB_MISC2_0;
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uint32_t _0xCC[1]; /* undefined */
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uint32_t EMEM_ARB_DA_TURNS_0; /* 0x D0 */
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uint32_t EMEM_ARB_DA_COVERS_0;
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uint32_t EMEM_ARB_MISC0_0;
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uint32_t EMEM_ARB_MISC1_0;
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uint32_t EMEM_ARB_RING1_THROTTLE_0; /* 0xE0 */
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uint32_t EMEM_ARB_RING3_THROTTLE_0;
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uint32_t EMEM_ARB_OVERRIDE_0;
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uint32_t EMEM_ARB_RSV_0;
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uint32_t _0xF0;
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uint32_t _0xF0[1]; /* undefined */ /* 0xF0 */
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uint32_t CLKEN_OVERRIDE_0;
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uint32_t _0xF8[76];
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uint32_t _0xF8[1]; /* undefined */
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uint32_t TIMING_CONTROL_0;
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uint32_t STAT_CONTROL_0; /* 0x100 */
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uint32_t _0x104[63]; /* undefined */
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uint32_t CLIENT_HOTRESET_CTRL_0; /* 0x200 */
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uint32_t CLIENT_HOTRESET_STATUS_0;
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uint32_t EMEM_ARB_ISOCHRONOUS_0_0;
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uint32_t EMEM_ARB_ISOCHRONOUS_1_0;
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uint32_t EMEM_ARB_ISOCHRONOUS_2_0; /* 0x210 */
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uint32_t EMEM_ARB_ISOCHRONOUS_3_0;
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uint32_t EMEM_ARB_HYSTERESIS_0_0;
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uint32_t EMEM_ARB_HYSTERESIS_1_0;
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uint32_t EMEM_ARB_HYSTERESIS_2_0; /* 0x220 */
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uint32_t EMEM_ARB_HYSTERESIS_3_0;
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uint32_t SMMU_TRANSLATION_ENABLE_0_0;
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uint32_t SMMU_TRANSLATION_ENABLE_1_0;
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uint32_t SMMU_TRANSLATION_ENABLE_2_0;
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uint32_t SMMU_TRANSLATION_ENABLE_2_0; /* 0x230 */
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uint32_t SMMU_TRANSLATION_ENABLE_3_0;
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uint32_t _0x234[1];
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uint32_t SMMU_AFI_ASID_0;
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uint32_t SMMU_AVPC_ASID_0;
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uint32_t _0x240[22];
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uint32_t SMMU_DC_ASID_0; /* 0x240 */
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uint32_t SMMU_DCB_ASID_0;
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uint32_t _0x228[2]; /* undefined */
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uint32_t SMMU_HC_ASID_0; /* 0x250 */
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uint32_t SMMU_HDA_ASID_0;
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uint32_t SMMU_ISP2_ASID_0;
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uint32_t _0x25C[2]; /* undefined */
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uint32_t SMMU_NVENC_ASID_0;
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uint32_t SMMU_NV_ASID_0;
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uint32_t SMMU_NV2_ASID_0;
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uint32_t SMMU_PPCS_ASID_0; /* 0x270 */
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uint32_t SMMU_SATA_ASID_0;
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uint32_t _0x278[2]; /* undefined */
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uint32_t SMMU_VI_ASID_0; /* 0x280 */
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uint32_t SMMU_VIC_ASID_0;
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uint32_t SMMU_XUSB_HOST_ASID_0;
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uint32_t SMMU_XUSB_DEV_ASID_0;
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uint32_t _0x290[1]; /* undefined */
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uint32_t SMMU_TSEC_ASID_0;
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uint32_t SMMU_PPCS1_ASID_0;
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uint32_t _0x29C[235];
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uint32_t _0x648;
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uint32_t _0x64C;
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uint32_t _0x650;
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uint32_t _0x654[2];
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uint32_t _0x65C;
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uint32_t _0x660;
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uint32_t _0x664[3];
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uint32_t SEC_CARVEOUT_BOM_0; /* [PMC_SECURE] Base address for the SEC carveout address space */
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uint32_t _0x29C[95]; /* undefined */
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uint32_t VIDEO_PROTECT_VPR_OVERRIDE_0;
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uint32_t _0x41C[93]; /* undefined */
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uint32_t VIDEO_PROTECT_VPR_OVERRIDE1_0; /* 0x590 */
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uint32_t _0x594[27]; /* undefined */
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uint32_t SMMU_TLB_SET_SELECTION_MASK_0_0; /* 0x600 */
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uint32_t _0x604[1]; /* undefined */
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uint32_t DISPLAY_SNAP_RING_0;
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uint32_t _0x648; /* unknown */
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uint32_t _0x64C; /* unknown */
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uint32_t _0x650; /* unknown */ /* 0x650 */
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uint32_t ERR_VPR_STATUS_0;
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uint32_t ERR_VPR_ADR_0;
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uint32_t _0x65C; /* unknown */
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uint32_t _0x660; /* unknown */ /* 0x660 */
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uint32_t EMEM_CFG_ACCESS_CTRL_0;
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uint32_t TZ_SECURITY_CTRL_0;
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uint32_t EMEM_ARB_OUTSTANDING_REQ_RING3_0; /* Access Control Bit for EMEM_CFG Registers - Sticky write access lock - 18.11.1.87 */
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uint32_t SEC_CARVEOUT_BOM_0; /* [PMC_SECURE] Base address for the SEC carveout address space */ /* 0x670 */
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uint32_t SEC_CARVEOUT_SIZE_MB_0; /* [PMC_SECURE] SEC_CARVEOUT_SIZE_MB is the size, in megabytes, of the SEC carveout region. If set to 0, the security check in MC is disabled */
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/* [PMC_SECURE] Sticky bit to control the writes to the other Sec Carveout aperture registers
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0 = Enabled
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1 = Disabled */
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1 = Disabled
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*/
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uint32_t SEC_CARVEOUT_REG_CTRL_0;
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uint32_t _0x67C[186];
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uint32_t EMEM_CFG_ACCESS_CTRL_0_AND_IRAM_REG_CTRL_0;
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uint32_t _0x968[7];
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uint32_t ERR_SEC_STATUS_0;
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uint32_t ERR_SEC_ADR_0; /* 0x680 */
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uint32_t PC_IDLE_CLOCK_GATE_CONFIG_0;
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uint32_t STUTTER_CONTROL_0;
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uint32_t _0x68C[9]; /* undefined */
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uint32_t EMEM_ARB_NISO_THROTTLE_0; /* 0x6B0 */
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uint32_t EMEM_ARB_OUTSTANDING_REQ_NISO_0;
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uint32_t EMEM_ARB_NISO_THROTTLE_MASK_0;
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uint32_t EMEM_ARB_RING0_THROTTLE_MASK_0;
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uint32_t EMEM_ARB_TIMING_RFCPB_0; /* 0x6C0 */
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uint32_t EMEM_ARB_TIMING_CCDMW_0;
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uint32_t _0x6C8[10]; /* undefined */
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uint32_t EMEM_ARB_REFPB_HP_CTRL_0; /* 0x6F0 */
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uint32_t EMEM_ARB_REFPB_BANK_CTRL_0;
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uint32_t _0x6F8[155]; /* undefined */
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uint32_t IRAM_REG_CTRL_0;
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uint32_t EMEM_ARB_OVERRIDE_1_0;
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uint32_t _0x96C[1]; /* undefined */
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uint32_t CLIENT_HOTRESET_CTRL_1_0; /* 0x970 */
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uint32_t CLIENT_HOTRESET_STATUS_1_0;
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uint32_t _0x978[3]; /* undefined */
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uint32_t VIDEO_PROTECT_GPU_OVERRIDE_0_0;
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uint32_t _0x988[6];
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uint32_t MTS_CARVEOUT_BOM_0;
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uint32_t VIDEO_PROTECT_GPU_OVERRIDE_1_0;
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uint32_t _0x98C[5]; /* undefined */
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uint32_t MTS_CARVEOUT_BOM_0; /* 0x9A0 */
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uint32_t MTS_CARVEOUT_SIZE_MB_0;
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uint32_t MTS_CARVEOUT_ADR_HI_0;
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/* MTS_CARVEOUT_WRITE_ACCESS
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0 = Enabled
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1 = Disabled */
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1 = Disabled
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*/
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uint32_t MTS_CARVEOUT_REG_CTRL_0;
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uint32_t _0x9B0[3];
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uint32_t _0x9B0[2]; /* undefined */ /* 0x9B0 */
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uint32_t SMMU_PTC_FLUSH_1_0;
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/* Base Address Higher Bits
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SECURITY_BOM_HI has the higher address bits beyond 32 bits of the
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base of the secured region, limited to MB granularity */
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uint32_t SECURITY_BOM_HI; /* MC_SECURITY_CFG3_0 */
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uint32_t _0x9C0[118];
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uint32_t SMMU_TRANSLATION_ENABLE_4_0;
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base of the secured region, limited to MB granularity
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*/
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uint32_t SECURITY_CFG3_0;
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uint32_t EMEM_BANK_SWIZZLE_CFG0_0; /* 0x9C0 */
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uint32_t EMEM_BANK_SWIZZLE_CFG1_0;
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uint32_t EMEM_BANK_SWIZZLE_CFG2_0;
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uint32_t EMEM_BANK_SWIZZLE_CFG3_0;
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uint32_t _0x9D0[1]; /* undefined */
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uint32_t SEC_CARVEOUT_ADR_HI_0;
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uint32_t _0x9D8[44]; /* undefined */
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uint32_t SMMU_DC1_ASID_0; /* 0xA88 */
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uint32_t _0xA8C[2]; /* undefined */
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uint32_t SMMU_SDMMC1A_ASID_0;
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uint32_t SMMU_SDMMC2A_ASID_0;
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uint32_t SMMU_SDMMC3A_ASID_0;
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uint32_t SMMU_SDMMC4A_ASID_0; /* 0xAA0 */
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uint32_t SMMU_ISP2B_ASID_0;
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uint32_t SMMU_GPU_ASID_0;
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uint32_t SMMU_GPUB_ASID_0;
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uint32_t SMMU_PPCS2_ASID_0; /* 0xAB0 */
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uint32_t SMMU_NVDEC_ASID_0;
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uint32_t SMMU_APE_ASID_0;
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uint32_t SMMU_SE_ASID_0;
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uint32_t SMMU_NVJPG_ASID_0; /* 0xAC0 */
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uint32_t SMMU_HC1_ASID_0;
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uint32_t SMMU_SE1_ASID_0;
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uint32_t SMMU_AXIAP_ASID_0;
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uint32_t SMMU_ETR_ASID_0; /* 0xAD0 */
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uint32_t SMMU_TSECB_ASID_0;
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uint32_t SMMU_TSEC1_ASID_0;
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uint32_t SMMU_TSECB1_ASID_0;
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uint32_t SMMU_NVDEC1_ASID_0; /* 0xAE0 */
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uint32_t _0xAE4[39]; /* undefined */
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uint32_t EMEM_ARB_NISO_THROTTLE_MASK_1_0; /* 0xB80 */
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uint32_t EMEM_ARB_HYSTERESIS_4_0;
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uint32_t _0xB88[3]; /* undefined */
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uint32_t EMEM_ARB_ISOCHRONOUS_4_0;
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uint32_t SMMU_TRANSLATION_ENABLE_4_0; /* 0xB98 */
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} mc_register_t; /* 0xB98 */
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volatile security_carveout_t *get_carveout_by_id(unsigned int carveout);
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@ -166,7 +166,7 @@ void warmboot_init(boot_func_list_t *func_list) {
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func_list->funcs.invalidate_icache_all();
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/* On warmboot (not cpu_on) only */
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if (MC_SECURITY_CFG3_0 == 0) {
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if (get_mc_reg()->SECURITY_CFG3_0 == 0) {
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init_dma_controllers(func_list->target_firmware);
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}
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@ -30,7 +30,7 @@ void __attribute__((noreturn)) warmboot_main(void) {
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identity_unmap_iram_cd_tzram();
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/* On warmboot (not cpu_on) only */
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if (get_mc_reg()->SECURITY_BOM_HI == 0) {
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if (get_mc_reg()->SECURITY_CFG3_0 == 0) {
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if (!configitem_is_retail()) {
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/* TODO: uart_log("OHAYO"); */
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}
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