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Merge branch 'master' of https://github.com/Atmosphere-NX/Atmosphere into logmanager

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XorTroll 2021-01-28 08:56:34 +01:00
commit 519bf31ec7
715 changed files with 59420 additions and 144918 deletions
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6
Makefile
View file

@ -101,14 +101,14 @@ dist-no-debug: all
touch atmosphere-$(AMSVER)/atmosphere/contents/0100000000000037/flags/boot2.flag
cp troposphere/reboot_to_payload/reboot_to_payload.nro atmosphere-$(AMSVER)/switch/reboot_to_payload.nro
cp troposphere/daybreak/daybreak.nro atmosphere-$(AMSVER)/switch/daybreak.nro
cd atmosphere-$(AMSVER); zip -r ../atmosphere-EXPERIMENTAL-$(AMSVER).zip ./*; cd ../;
cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../;
cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/atmosphere/fusee-secondary.bin
cp fusee/fusee-secondary/fusee-secondary.bin atmosphere-$(AMSVER)/sept/payload.bin
cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER).zip ./*; cd ../;
cd atmosphere-$(AMSVER); zip -r ../atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip ./*; cd ../;
rm -r atmosphere-$(AMSVER)
mkdir out
mv atmosphere-EXPERIMENTAL-$(AMSVER).zip out/atmosphere-EXPERIMENTAL-$(AMSVER).zip
mv atmosphere-$(AMSVER).zip out/atmosphere-$(AMSVER).zip
mv atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip out/atmosphere-$(AMSVER)-WITHOUT_MESOSPHERE.zip
cp fusee/fusee-primary/fusee-primary.bin out/fusee-primary.bin
dist: dist-no-debug

10
docs/building.md
View file

@ -5,6 +5,7 @@ Building Atmosphère is a very straightforward process that relies almost exclus
+ [devkitA64](https://devkitpro.org)
+ [devkitARM](https://devkitpro.org)
+ [Python 2](https://www.python.org) (Python 3 may work as well, but this is not guaranteed)
+ [LZ4](https://pypi.org/project/lz4)
+ [PyCryptodome](https://pypi.org/project/pycryptodome) (optional)
## Instructions
@ -17,12 +18,15 @@ Building Atmosphère is a very straightforward process that relies almost exclus
+ `devkitARM`
+ `devkitarm-rules`
3. (Optional) In order to build [sept](components/sept.md) the pycryptodome PyPi package is required, which can be installed by running `pip install pycryptodome` under the installed Python environment of your choice or by installing the complete zip package to support the `make dist` recipe. This is an optional step included for advanced users who have the ability to provide the necessary encryption/signing keys themselves.
3. Install the following library via python's package manager `pip`, required by [exosphere](components/exosphere.md):
+ `lz4`
4. It is, instead, possible to build [sept](components/sept.md) by providing previously encrypted/signed binaries distributed by official Atmosphère release packages. In order to do so, export the following variables in your current environment:
4. (Optional) In order to build [sept](components/sept.md) the pycryptodome PyPi package is required, which can be installed by running `pip install pycryptodome` under the installed Python environment of your choice or by installing the complete zip package to support the `make dist` recipe. This is an optional step included for advanced users who have the ability to provide the necessary encryption/signing keys themselves.
5. It is, instead, possible to build [sept](components/sept.md) by providing previously encrypted/signed binaries distributed by official Atmosphère release packages. In order to do so, export the following variables in your current environment:
+ `SEPT_00_ENC_PATH` (must point to the `sept-secondary_00.enc` file)
+ `SEPT_01_ENC_PATH` (must point to the `sept-secondary_01.enc` file)
+ `SEPT_DEV_00_ENC_PATH` (must point to the `sept-secondary_dev_00.enc` file)
+ `SEPT_DEV_01_ENC_PATH` (must point to the `sept-secondary_dev_01.enc` file)
5. Finally, clone the Atmosphère repository and run `make` under its root directory.
6. Finally, clone the Atmosphère repository and run `make` under its root directory.

25
docs/changelog.md
View file

@ -1,4 +1,29 @@
# Changelog
## 0.17.1
+ A number of atmosphère's modules were using more memory than their Nintendo equivalent's in 0.17.0; a number of code generatio tweaks have been applied to fix this across the board.
+ A detailed comparison of atmosphère module memory usage versus Nintendo's was made and can be found [here](https://github.com/Atmosphere-NX/Atmosphere/wiki/Memory-Comparisons).
+ Several minor bugs were fixed, including:
+ A bug was fixed in mesosphère that caused games which attempt to map more memory than the Switch has to fail.
+ This affected "Piczle Lines DX 500 More Puzzles!", and possibly other games.
+ Enabling configuration to "blank" PRODINFO no longer causes a hang on Mariko devices (or any devices with newer format).
+ Several issues were fixed, and usability and stability were improved.
## 0.17.0
+ fusee was heavily rewritten in order to add support for Mariko hardware.
+ **Please Note**: Mariko hardware currently has no (and may not ever have any) software exploits; fusee works when loaded from bootloader context with the right keys in the security engine. No means of getting the system into this state is provided.
+ An issue was fixed in the way shutdown was performed on Erista hardware.
+ This fixes an issue that caused OFW to black screen on boot after power off from atmosphere without first doing a reboot.
+ This also substantially improves power drain when the system is shut off; consoles powered off from Atmosphere should now drain battery at the same reduced rate as original firmware.
+ A number of minor changes were made, including:
+ A number of inconsistencies in the build system were fixed.
+ Fow those building atmosphère at home, the `boot` sysmodule will no longer rebuild every time make is invoked.
+ This substantially improves build times during development iteration.
+ `sm` was updated to more accurately reflect how official code manages request deferral.
+ `mesosphère` was updated to more accurately reflect official kernel management of the trace buffer.
+ `mesosphère` was updated to improve kernel loader's logic by taking advantage of the assumption that we only boot our kernel, not Nintendo's.
+ As it has been a few months with zero reported issues, `mesosphère` is now opt-out.
+ Users who wish to begin using or continue using mesosphere should use the standard/cool kids zip ("atmosphere-").
+ Users who wish to opt-out of mesosphere should download and extract the opt-out zip ("atmosphere-WITHOUT_MESOSPHERE-").
+ Several issues were fixed, and usability and stability were improved.
## 0.16.2
+ Atmosphère release zips no longer bundle BCT.ini, instead relying on defaults in code.
+ This means atmosphere updates should no longer overwrite any user configuration at all.

40
docs/roadmap.md
View file

@ -1,42 +1,32 @@
# Planned Features
atmosphère has a number of features that are either works-in-progress or planned. Please note that while time-estimates are given, they are loose, and things may be completed sooner or later than advertised.
The following descriptions were last updated on July 7th, 2020.
## ams-on-mariko
* **Description**: Atmosphere cannot run as-is on Mariko hardware. A large number of changes are needed in many components. Although secure monitor support is complete in exosphere, additional work is needed on the bootloader and stratosphere sides as well. Mariko support will also require further design thought; atmosphere's debugging design heavily relies on reboot-to-payload and (more generally) the ability to perform warmboot bootrom hax at will. This is not possible on Mariko, and will require a new design/software support for whatever solution is chosen.
* **Development Status**: Planned.
* **Estimated Time**: Summer 2020
## settings reimplementation
* **Description**: A planned reimplementation of the settings system module, and with it a removal of the settings mitm. This will greatly simplify atmosphère's boot process, and will allow much more flexible control over the various system settings.
* **Development Status**: Undergoing research/initial development by Adubbz.
* **Estimated Time**: Mid 2020
## mesosphere
* **Description**: mesosphère is a reimplementation of the Horizon operating system's Kernel. It aims to provide an open-source reference for Nintendo's code.
* **Development Status**: Under active development by SciresM.
* **Estimated Time**: Mid-to-Late 2020
The following descriptions were last updated on January 14th, 2021
## tma reimplementation
* **Description** tma ("target manager agent") is a system module that manages communication between the Switch and a client PC. Atmosphere's implementation will allow homebrew on the switch to communicate with a connected PC to do various operations such as exchanging data or interacting with files. It will also serve as the communicator for Atmosphère's planned debugger. This will also include PC-side software for interacting with the Switch.
* **Development Status**: Planned. Switch-side code is fully implemented but needs heavy refactoring/rebasing, as the code was originally authored in 2018.
* **Estimated Time**: Late 2020-2021.
* **Estimated Time**: 2021-2022.
## dmnt.gen2 reimplementation
* **Description**: A reimplementation of the Switch's debug monitor, dmnt will provide an interface for debugging applications or system modules running on the Switch. This will include a gdbstub for debugging actively-running system components or applications.
* **Development Status**: Planned
* **Estimated Time**: 2021
* **Estimated Time**: 2021-2022
## fs reimplementation
* **Description**: Following mesosphère's completion, atmosphère will have reimplemented all components of the BootImagePackage firmware except for the filesystem services system module. Reimplementing fs will allow for fixing Nintendo bugs (such as corruption when using exFAT filesystems and encoding inconsistencies with UTF-8 and Shift-JIS).
* **Development Status**: Planned.
* **Estimated Time**: 2021-2022.
## settings reimplementation
* **Description**: A planned reimplementation of the settings system module, and with it a removal of the settings mitm. This will greatly simplify atmosphère's boot process, and will allow much more flexible control over the various system settings.
* **Development Status**: Pending development by Adubbz.
* **Estimated Time**: Unclear, pending developer availability.
## thermosphère
* **Description**: A general-purpose hypervisor, thermosphère will enable the virtualization of the Switch's operating system; this is planned to enable debugging of the Switch's kernel.
* **Development Status**: Under semi-active development by TuxSH.
* **Estimated Time**: 2020-2021.
* **Development Status**: Pending development by TuxSH.
* **Estimated Time**: Unclear, pending developer availability.
## other planned features
* **Description**: General system stability improvements to enhance the user's experience.
@ -59,4 +49,12 @@ Please note that this is not an exhaustive list of features present in atmosphè
## exosphere re-write
* **Description**: exosphère, atmosphère's reimplementation of Horizon's Secure Monitor, was the first component authored for the project in early 2018. It is written in C, and in a style very different from the rest of atmosphère's code. In addition, exosphère was written to conform to constraints that no longer apply in an environment where it is not launched from the web browser, and where using a custom firmware image to orchestrate wake-from-sleep is possible. exosphère currently uses all but 1 KB of the space available to it, putting it at risk of breaking as future firmware updates are supported. A re-write will solve these issues.
* **Completion Time**: June 2020
* **Completion Time**: June 2020
## mesosphere
* **Description**: mesosphère is a reimplementation of the Horizon operating system's Kernel. It aims to provide an open-source reference for Nintendo's code.
* **Estimated Time**: September 2020
## ams-on-mariko
* **Description**: Atmosphere cannot run as-is on Mariko hardware. A large number of changes are needed in many components. Although secure monitor support is complete in exosphere, additional work is needed on the bootloader and stratosphere sides as well. Mariko support will also require further design thought; atmosphere's debugging design heavily relies on reboot-to-payload and (more generally) the ability to perform warmboot bootrom hax at will. This is not possible on Mariko, and will require a new design/software support for whatever solution is chosen.
* **Completion Time**: January 2021

2
exosphere/loader_stub/Makefile
View file

@ -120,7 +120,7 @@ $(OFILES) : $(ATMOSPHERE_LIBRARIES_DIR)/libexosphere/$(ATMOSPHERE_LIBRARY_DIR)/l
program.lz4.o: program_lz4.h
program.lz4.o program_lz4.h: $(TOPDIR)/../program/program$(ATMOSPHERE_BUILD_TARGET_BINARY_SUFFIX).lz4
program_lz4.h: $(TOPDIR)/../program/program$(ATMOSPHERE_BUILD_TARGET_BINARY_SUFFIX).lz4
@echo $(notdir $<)
@rm -rf tmp_program_$(ATMOSPHERE_BUILD_TARGET_IDENTIFIER)
@mkdir -p tmp_program_$(ATMOSPHERE_BUILD_TARGET_IDENTIFIER)

10
exosphere/mariko_fatal/source/fatal_display.cpp
View file

@ -111,7 +111,7 @@ namespace ams::secmon::fatal {
}
}
void EnableBacklightForVendor2050ForHardwareTypeFive(int brightness) {
void EnableBacklightForVendor2050ForAula(int brightness) {
/* Enable FRAME_END_INT */
reg::Write(g_disp1_regs + sizeof(u32) * DC_CMD_INT_ENABLE, 2);
@ -270,7 +270,7 @@ namespace ams::secmon::fatal {
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_RST, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
if (fuse::GetHardwareType() == fuse::HardwareType_Five) {
if (fuse::GetHardwareType() == fuse::HardwareType_Aula) {
/* Configure LCD backlight. */
reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x4);
reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x4);
@ -384,7 +384,7 @@ namespace ams::secmon::fatal {
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_BL_EN, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
reg::ClearBits(g_apb_misc_regs + PINMUX_AUX_LCD_RST, reg::EncodeMask(PINMUX_REG_BITS_MASK(AUX_TRISTATE)));
if (hw_type == fuse::HardwareType_Five) {
if (hw_type == fuse::HardwareType_Aula) {
/* Configure LCD backlight. */
reg::SetBits(g_gpio_regs + GPIO_PORT6_CNF_1, 0x4);
reg::SetBits(g_gpio_regs + GPIO_PORT6_OE_1, 0x4);
@ -429,7 +429,7 @@ namespace ams::secmon::fatal {
reg::SetBits(g_gpio_regs + GPIO_PORT6_OUT_1, 0x4);
util::WaitMicroSeconds(60'000ul);
if (hw_type == fuse::HardwareType_Five) {
if (hw_type == fuse::HardwareType_Aula) {
reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x40103);
} else {
reg::Write(g_dsi_regs + sizeof(u32) * DSI_BTA_TIMING, 0x50204);
@ -593,7 +593,7 @@ namespace ams::secmon::fatal {
/* Enable backlight. */
constexpr auto DisplayBrightness = 100;
if (GetLcdVendor() == 0x2050) {
EnableBacklightForVendor2050ForHardwareTypeFive(DisplayBrightness);
EnableBacklightForVendor2050ForAula(DisplayBrightness);
} else {
EnableBacklightForGeneric(DisplayBrightness);
}

14
exosphere/program/source/boot/secmon_boot_setup.cpp
View file

@ -64,17 +64,9 @@ namespace ams::secmon::boot {
/* Configure warmboot to set Set FUSE_PRIVATEKEYDISABLE to KEY_INVISIBLE. */
reg::ReadWrite(pmc + APBDEV_PMC_SECURE_SCRATCH21, REG_BITS_VALUE(4, 1, 1));
/* Write the warmboot key. */
/* TODO: This is necessary for mariko. We should decide how to handle this. */
/* In particular, mariko will need to support loading older-than-expected warmboot firmware. */
/* We could hash the warmboot firmware and use a lookup table, or require bootloader to provide */
/* The warmboot key as a parameter. The latter is a better solution, but it would be nice to take */
/* care of it here. Perhaps we should read the number of anti-downgrade fuses burnt, and translate that */
/* to the warmboot key? To be decided during the process of implementing ams-on-mariko support. */
reg::Write(pmc + APBDEV_PMC_SECURE_SCRATCH32, 0x129);
/* TODO: Fix to ensure correct scratch contents on mariko, as otherwise wb is broken. */
AMS_ABORT_UNLESS(fuse::GetSocType() != fuse::SocType_Mariko);
/* NOTE: Here, Nintendo writes the warmboot key. */
/* However, we rely on the bootloader (e.g. fusee/hekate) having already done this. */
/* reg::Write(pmc + APBDEV_PMC_SECURE_SCRATCH32, ...); */
}
/* This function derives the master kek and device keys using the tsec root key. */

4
exosphere/program/source/secmon_setup.cpp
View file

@ -409,8 +409,8 @@ namespace ams::secmon {
reg0 |= reg::Encode(SLAVE_SECURITY_REG_BITS_ENUM(0, CEC, ENABLE));
}
/* Icosa, Iowa, and Five all set I2C4 to be secure. */
if (hw_type == fuse::HardwareType_Icosa && hw_type == fuse::HardwareType_Iowa && hw_type == fuse::HardwareType_Five) {
/* Icosa, Iowa, and Aula all set I2C4 to be secure. */
if (hw_type == fuse::HardwareType_Icosa && hw_type == fuse::HardwareType_Iowa && hw_type == fuse::HardwareType_Aula) {
reg1 |= reg::Encode(SLAVE_SECURITY_REG_BITS_ENUM(1, I2C4, ENABLE));
}

10
exosphere/program/source/smc/secmon_smc_info.cpp
View file

@ -47,7 +47,7 @@ namespace ams::secmon::smc {
[fuse::DramId_IcosaSamsung4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_IcosaHynix4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_IcosaMicron4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_FiveHynix1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_AulaHynix1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_IcosaSamsung6GB] = pkg1::MemorySize_6GB,
[fuse::DramId_CopperHynix4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_CopperMicron4GB] = pkg1::MemorySize_4GB,
@ -66,13 +66,13 @@ namespace ams::secmon::smc {
[fuse::DramId_HoagSamsung1y4GBX] = pkg1::MemorySize_4GB,
[fuse::DramId_IowaSamsung1y4GBY] = pkg1::MemorySize_4GB,
[fuse::DramId_IowaSamsung1y8GBY] = pkg1::MemorySize_8GB,
[fuse::DramId_FiveSamsung1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_AulaSamsung1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_HoagSamsung1y8GBX] = pkg1::MemorySize_8GB,
[fuse::DramId_FiveSamsung1y4GBX] = pkg1::MemorySize_4GB,
[fuse::DramId_AulaSamsung1y4GBX] = pkg1::MemorySize_4GB,
[fuse::DramId_IowaMicron1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_HoagMicron1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_FiveMicron1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_FiveSamsung1y8GBX] = pkg1::MemorySize_8GB,
[fuse::DramId_AulaMicron1y4GB] = pkg1::MemorySize_4GB,
[fuse::DramId_AulaSamsung1y8GBX] = pkg1::MemorySize_8GB,
};
constexpr const pkg1::MemoryMode MemoryModes[] = {

0
fusee/fusee-mtc/src/display/cfb_console.c → fusee/common/display/cfb_console.c
View file

0
fusee/fusee-secondary/src/display/video_fb.h → fusee/common/display/video_fb.h
View file

0
fusee/fusee-mtc/src/display/video_font_large.h → fusee/common/display/video_font_large.h
View file

0
fusee/fusee-mtc/src/display/video_font_small.h → fusee/common/display/video_font_small.h
View file

10
fusee/fusee-primary/src/lib/fatfs/00history.txt → fusee/common/fatfs/00history.txt
View file

@ -328,3 +328,13 @@ R0.13c (October 14, 2018)
Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
R0.14 (October 14, 2019)
Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1)
Changed some API functions, f_mkfs() and f_fdisk().
Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters.
Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12)
Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12)

2
fusee/fusee-primary/src/lib/fatfs/00readme.txt → fusee/common/fatfs/00readme.txt
View file

@ -1,4 +1,4 @@
FatFs Module Source Files R0.13c
FatFs Module Source Files R0.14
FILES

51
fusee/fusee-secondary/src/lib/fatfs/diskio.c → fusee/common/fatfs/diskio.c
View file

@ -1,5 +1,5 @@
/*-----------------------------------------------------------------------*/
/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2019 */
/*-----------------------------------------------------------------------*/
/* If a working storage control module is available, it should be */
/* attached to the FatFs via a glue function rather than modifying it. */
@ -12,10 +12,20 @@
#include "ff.h" /* Obtains integer types */
#include "diskio.h" /* Declarations of disk functions */
#include "ffconf.h"
#include "../../device_partition.h"
#if defined(FUSEE_STAGE1_SRC)
#include "../../../fusee/fusee-primary/fusee-primary-main/src/fs_utils.h"
#elif defined(FUSEE_STAGE2_SRC)
#include "../../../fusee/fusee-secondary/src/device_partition.h"
#elif defined(SEPT_STAGE2_SRC)
#include "../../../sept/sept-secondary/src/fs_utils.h"
#endif
#ifdef FUSEE_STAGE2_SRC
/* fs_dev.c */
extern device_partition_t *g_volume_to_devparts[FF_VOLUMES];
#endif
/*-----------------------------------------------------------------------*/
/* Get Drive Status */
@ -25,11 +35,15 @@ DSTATUS disk_status (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
#ifdef FUSEE_STAGE2_SRC
device_partition_t *devpart = g_volume_to_devparts[pdrv];
if (devpart)
return devpart->initialized ? RES_OK : STA_NOINIT;
else
return STA_NODISK;
#else
return RES_OK;
#endif
}
@ -42,14 +56,18 @@ DSTATUS disk_initialize (
BYTE pdrv /* Physical drive nmuber to identify the drive */
)
{
#ifdef FUSEE_STAGE2_SRC
/* We aren't using FF_MULTI_PARTITION, so pdrv = volume id. */
device_partition_t *devpart = g_volume_to_devparts[pdrv];
if (!devpart)
return STA_NODISK;
else if (devpart->initializer)
return devpart->initializer(devpart) ? STA_NOINIT : RES_OK;
else
else
return RES_OK;
#else
return RES_OK;
#endif
}
@ -61,10 +79,11 @@ DSTATUS disk_initialize (
DRESULT disk_read (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
BYTE *buff, /* Data buffer to store read data */
DWORD sector, /* Start sector in LBA */
LBA_t sector, /* Start sector in LBA */
UINT count /* Number of sectors to read */
)
{
#ifdef FUSEE_STAGE2_SRC
/* We aren't using FF_MULTI_PARTITION, so pdrv = volume id. */
device_partition_t *devpart = g_volume_to_devparts[pdrv];
if (!devpart)
@ -73,6 +92,14 @@ DRESULT disk_read (
return device_partition_read_data(devpart, buff, sector, count) ? RES_ERROR : RES_OK;
else
return RES_ERROR;
#else
switch (pdrv) {
case 0:
return sdmmc_device_read(&g_sd_device, sector, count, (void *)buff) ? RES_OK : RES_ERROR;
default:
return RES_PARERR;
}
#endif
}
@ -86,10 +113,11 @@ DRESULT disk_read (
DRESULT disk_write (
BYTE pdrv, /* Physical drive nmuber to identify the drive */
const BYTE *buff, /* Data to be written */
DWORD sector, /* Start sector in LBA */
LBA_t sector, /* Start sector in LBA */
UINT count /* Number of sectors to write */
)
{
#ifdef FUSEE_STAGE2_SRC
/* We aren't using FF_MULTI_PARTITION, so pdrv = volume id. */
device_partition_t *devpart = g_volume_to_devparts[pdrv];
if (!devpart)
@ -98,6 +126,14 @@ DRESULT disk_write (
return device_partition_write_data(devpart, buff, sector, count) ? RES_ERROR : RES_OK;
else
return RES_ERROR;
#else
switch (pdrv) {
case 0:
return sdmmc_device_write(&g_sd_device, sector, count, (void *)buff) ? RES_OK : RES_ERROR;
default:
return RES_PARERR;
}
#endif
}
#endif
@ -113,6 +149,8 @@ DRESULT disk_ioctl (
void *buff /* Buffer to send/receive control data */
)
{
#ifdef FUSEE_STAGE2_SRC
/* We aren't using FF_MULTI_PARTITION, so pdrv = volume id. */
device_partition_t *devpart = g_volume_to_devparts[pdrv];
switch (cmd) {
case GET_SECTOR_SIZE:
@ -121,5 +159,8 @@ DRESULT disk_ioctl (
default:
return RES_OK;
}
#else
return RES_OK;
#endif
}

77
fusee/common/fatfs/diskio.h Normal file
View file

@ -0,0 +1,77 @@
/*-----------------------------------------------------------------------/
/ Low level disk interface modlue include file (C)ChaN, 2019 /
/-----------------------------------------------------------------------*/
#ifndef _DISKIO_DEFINED
#define _DISKIO_DEFINED
#ifdef __cplusplus
extern "C" {
#endif
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*---------------------------------------*/
/* Prototypes for disk control functions */
DSTATUS disk_initialize (BYTE pdrv);
DSTATUS disk_status (BYTE pdrv);
DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01 /* Drive not initialized */
#define STA_NODISK 0x02 /* No medium in the drive */
#define STA_PROTECT 0x04 /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (Used by FatFs) */
#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
/* Generic command (Not used by FatFs) */
#define CTRL_POWER 5 /* Get/Set power status */
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
#define CTRL_EJECT 7 /* Eject media */
#define CTRL_FORMAT 8 /* Create physical format on the media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10 /* Get card type */
#define MMC_GET_CSD 11 /* Get CSD */
#define MMC_GET_CID 12 /* Get CID */
#define MMC_GET_OCR 13 /* Get OCR */
#define MMC_GET_SDSTAT 14 /* Get SD status */
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20 /* Get F/W revision */
#define ATA_GET_MODEL 21 /* Get model name */
#define ATA_GET_SN 22 /* Get serial number */
#ifdef __cplusplus
}
#endif
#endif

6864
fusee/common/fatfs/ff.c Normal file
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426
fusee/common/fatfs/ff.h Normal file
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@ -0,0 +1,426 @@
/*----------------------------------------------------------------------------/
/ FatFs - Generic FAT Filesystem module R0.14 /
/-----------------------------------------------------------------------------/
/
/ Copyright (C) 2019, ChaN, all right reserved.
/
/ FatFs module is an open source software. Redistribution and use of FatFs in
/ source and binary forms, with or without modification, are permitted provided
/ that the following condition is met:
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/
/----------------------------------------------------------------------------*/
#ifndef FF_DEFINED
#define FF_DEFINED 86606 /* Revision ID */
#ifdef __cplusplus
extern "C" {
#endif
#include "ffconf.h" /* FatFs configuration options */
#if FF_DEFINED != FFCONF_DEF
#error Wrong configuration file (ffconf.h).
#endif
/* Integer types used for FatFs API */
#if defined(_WIN32) /* Main development platform */
#define FF_INTDEF 2
#include <windows.h>
typedef unsigned __int64 QWORD;
#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */
#define FF_INTDEF 2
#include <stdint.h>
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */
typedef uint16_t WORD; /* 16-bit unsigned integer */
typedef uint32_t DWORD; /* 32-bit unsigned integer */
typedef uint64_t QWORD; /* 64-bit unsigned integer */
typedef WORD WCHAR; /* UTF-16 character type */
#else /* Earlier than C99 */
#define FF_INTDEF 1
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */
typedef unsigned short WORD; /* 16-bit unsigned integer */
typedef unsigned long DWORD; /* 32-bit unsigned integer */
typedef WORD WCHAR; /* UTF-16 character type */
#endif
/* Definitions of volume management */
#if FF_MULTI_PARTITION /* Multiple partition configuration */
typedef struct {
BYTE pd; /* Physical drive number */
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
} PARTITION;
extern PARTITION VolToPart[]; /* Volume - Partition mapping table */
#endif
#if FF_STR_VOLUME_ID
#ifndef FF_VOLUME_STRS
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
#endif
#endif
/* Type of path name strings on FatFs API */
#ifndef _INC_TCHAR
#define _INC_TCHAR
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
typedef WCHAR TCHAR;
#define _T(x) L ## x
#define _TEXT(x) L ## x
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
typedef char TCHAR;
#define _T(x) u8 ## x
#define _TEXT(x) u8 ## x
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
typedef DWORD TCHAR;
#define _T(x) U ## x
#define _TEXT(x) U ## x
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
#error Wrong FF_LFN_UNICODE setting
#else /* ANSI/OEM code in SBCS/DBCS */
typedef char TCHAR;
#define _T(x) x
#define _TEXT(x) x
#endif
#endif
/* Type of file size and LBA variables */
#if FF_FS_EXFAT
#if FF_INTDEF != 2
#error exFAT feature wants C99 or later
#endif
typedef QWORD FSIZE_t;
#if FF_LBA64
typedef QWORD LBA_t;
#else
typedef DWORD LBA_t;
#endif
#else
#if FF_LBA64
#error exFAT needs to be enabled when enable 64-bit LBA
#endif
typedef DWORD FSIZE_t;
typedef DWORD LBA_t;
#endif
/* Filesystem object structure (FATFS) */
typedef struct {
BYTE fs_type; /* Filesystem type (0:not mounted) */
BYTE pdrv; /* Associated physical drive */
BYTE n_fats; /* Number of FATs (1 or 2) */
BYTE wflag; /* win[] flag (b0:dirty) */
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
WORD id; /* Volume mount ID */
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
WORD csize; /* Cluster size [sectors] */
#if FF_MAX_SS != FF_MIN_SS
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
#endif
#if FF_USE_LFN
WCHAR* lfnbuf; /* LFN working buffer */
#endif
#if FF_FS_EXFAT
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
#endif
#if FF_FS_REENTRANT
FF_SYNC_t sobj; /* Identifier of sync object */
#endif
#if !FF_FS_READONLY
DWORD last_clst; /* Last allocated cluster */
DWORD free_clst; /* Number of free clusters */
#endif
#if FF_FS_RPATH
DWORD cdir; /* Current directory start cluster (0:root) */
#if FF_FS_EXFAT
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
#endif
#endif
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
DWORD fsize; /* Size of an FAT [sectors] */
LBA_t volbase; /* Volume base sector */
LBA_t fatbase; /* FAT base sector */
LBA_t dirbase; /* Root directory base sector/cluster */
LBA_t database; /* Data base sector */
#if FF_FS_EXFAT
LBA_t bitbase; /* Allocation bitmap base sector */
#endif
LBA_t winsect; /* Current sector appearing in the win[] */
BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
} FATFS;
/* Object ID and allocation information (FFOBJID) */
typedef struct {
FATFS* fs; /* Pointer to the hosting volume of this object */
WORD id; /* Hosting volume mount ID */
BYTE attr; /* Object attribute */
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
#if FF_FS_EXFAT
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
#endif
#if FF_FS_LOCK
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
#endif
} FFOBJID;
/* File object structure (FIL) */
typedef struct {
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
BYTE flag; /* File status flags */
BYTE err; /* Abort flag (error code) */
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */
#if !FF_FS_READONLY
LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
#endif
#if FF_USE_FASTSEEK
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
#endif
#if !FF_FS_TINY
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
#endif
} FIL;
/* Directory object structure (DIR) */
typedef struct {
FFOBJID obj; /* Object identifier */
DWORD dptr; /* Current read/write offset */
DWORD clust; /* Current cluster */
LBA_t sect; /* Current sector (0:Read operation has terminated) */
BYTE* dir; /* Pointer to the directory item in the win[] */
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
#if FF_USE_LFN
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
#endif
#if FF_USE_FIND
const TCHAR* pat; /* Pointer to the name matching pattern */
#endif
} DIR;
/* File information structure (FILINFO) */
typedef struct {
FSIZE_t fsize; /* File size */
WORD fdate; /* Modified date */
WORD ftime; /* Modified time */
BYTE fattrib; /* File attribute */
#if FF_USE_LFN
TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
#else
TCHAR fname[12 + 1]; /* File name */
#endif
} FILINFO;
/* Format parameter structure (MKFS_PARM) */
typedef struct {
BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
BYTE n_fat; /* Number of FATs */
UINT align; /* Data area alignment (sector) */
UINT n_root; /* Number of root directory entries */
DWORD au_size; /* Cluster size (byte) */
} MKFS_PARM;
/* File function return code (FRESULT) */
typedef enum {
FR_OK = 0, /* (0) Succeeded */
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
FR_INT_ERR, /* (2) Assertion failed */
FR_NOT_READY, /* (3) The physical drive cannot work */
FR_NO_FILE, /* (4) Could not find the file */
FR_NO_PATH, /* (5) Could not find the path */
FR_INVALID_NAME, /* (6) The path name format is invalid */
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
FR_EXIST, /* (8) Access denied due to prohibited access */
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
FR_NOT_ENABLED, /* (12) The volume has no work area */
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
} FRESULT;
/*--------------------------------------------------------------*/
/* FatFs module application interface */
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
FRESULT f_close (FIL* fp); /* Close an open file object */
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
FRESULT f_truncate (FIL* fp); /* Truncate the file */
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
FRESULT f_closedir (DIR* dp); /* Close an open directory */
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */
FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */
FRESULT f_setcp (WORD cp); /* Set current code page */
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
#define f_error(fp) ((fp)->err)
#define f_tell(fp) ((fp)->fptr)
#define f_size(fp) ((fp)->obj.objsize)
#define f_rewind(fp) f_lseek((fp), 0)
#define f_rewinddir(dp) f_readdir((dp), 0)
#define f_rmdir(path) f_unlink(path)
#define f_unmount(path) f_mount(0, path, 0)
#ifndef EOF
#define EOF (-1)
#endif
/*--------------------------------------------------------------*/
/* Additional user defined functions */
/* RTC function */
#if !FF_FS_READONLY && !FF_FS_NORTC
DWORD get_fattime (void);
#endif
/* LFN support functions */
#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
#endif
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
void* ff_memalloc (UINT msize); /* Allocate memory block */
void ff_memfree (void* mblock); /* Free memory block */
#endif
/* Sync functions */
#if FF_FS_REENTRANT
int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
#endif
/*--------------------------------------------------------------*/
/* Flags and offset address */
/* File access mode and open method flags (3rd argument of f_open) */
#define FA_READ 0x01
#define FA_WRITE 0x02
#define FA_OPEN_EXISTING 0x00
#define FA_CREATE_NEW 0x04
#define FA_CREATE_ALWAYS 0x08
#define FA_OPEN_ALWAYS 0x10
#define FA_OPEN_APPEND 0x30
/* Fast seek controls (2nd argument of f_lseek) */
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
/* Format options (2nd argument of f_mkfs) */
#define FM_FAT 0x01
#define FM_FAT32 0x02
#define FM_EXFAT 0x04
#define FM_ANY 0x07
#define FM_SFD 0x08
/* Filesystem type (FATFS.fs_type) */
#define FS_FAT12 1
#define FS_FAT16 2
#define FS_FAT32 3
#define FS_EXFAT 4
/* File attribute bits for directory entry (FILINFO.fattrib) */
#define AM_RDO 0x01 /* Read only */
#define AM_HID 0x02 /* Hidden */
#define AM_SYS 0x04 /* System */
#define AM_DIR 0x10 /* Directory */
#define AM_ARC 0x20 /* Archive */
#ifdef __cplusplus
}
#endif
#endif /* FF_DEFINED */

165
fusee/fusee-secondary/src/lib/fatfs/ffconf.h → fusee/common/fatfs/ffconf.h
View file

@ -2,20 +2,20 @@
/ FatFs Functional Configurations
/---------------------------------------------------------------------------*/
#define FFCONF_DEF 86604 /* Revision ID */
#define FFCONF_DEF 86606 /* Revision ID */
/*---------------------------------------------------------------------------/
/ Function Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_READONLY 0
#define FF_FS_READONLY 0
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define FF_FS_MINIMIZE 0
#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: Basic functions are fully enabled.
@ -25,7 +25,7 @@
/ 3: f_lseek() function is removed in addition to 2. */
#define FF_USE_STRFUNC 2
#define FF_USE_STRFUNC 2
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
/
/ 0: Disable string functions.
@ -33,34 +33,38 @@
/ 2: Enable with LF-CRLF conversion. */
#define FF_USE_FIND 0
#define FF_USE_FIND 0
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#define FF_USE_MKFS 0
#define FF_USE_MKFS 0
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define FF_USE_FASTSEEK 0
#define FF_USE_FASTSEEK 0
/* This option switches fast seek function. (0:Disable or 1:Enable) */
#define FF_USE_EXPAND 0
#define FF_USE_EXPAND 0
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#define FF_USE_CHMOD 1
#ifdef FUSEE_STAGE2_SRC
#define FF_USE_CHMOD 1
#else
#define FF_USE_CHMOD 0
#endif
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
#define FF_USE_LABEL 0
#define FF_USE_LABEL 0
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define FF_USE_FORWARD 0
#define FF_USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
@ -68,7 +72,7 @@
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define FF_CODE_PAGE 850
#define FF_CODE_PAGE 850
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect code page setting can cause a file open failure.
/
@ -97,12 +101,12 @@
*/
#define FF_USE_LFN 1
#define FF_MAX_LFN 255
#define FF_USE_LFN 1
#define FF_MAX_LFN 255
/* The FF_USE_LFN switches the support for LFN (long file name).
/
/ 0: Disable LFN. FF_MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
@ -110,14 +114,14 @@
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
/ specification.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree() in ffsystem.c, need to be added to the project. */
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
#define FF_LFN_UNICODE 2
#define FF_LFN_UNICODE 2
/* This option switches the character encoding on the API when LFN is enabled.
/
/ 0: ANSI/OEM in current CP (TCHAR = char)
@ -129,15 +133,15 @@
/ When LFN is not enabled, this option has no effect. */
#define FF_LFN_BUF 255
#define FF_SFN_BUF 12
#define FF_LFN_BUF 255
#define FF_SFN_BUF 12
/* This set of options defines size of file name members in the FILINFO structure
/ which is used to read out directory items. These values should be suffcient for
/ the file names to read. The maximum possible length of the read file name depends
/ on character encoding. When LFN is not enabled, these options have no effect. */
#define FF_STRF_ENCODE 3
#define FF_STRF_ENCODE 3
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
/ This option selects assumption of character encoding ON THE FILE to be
@ -150,7 +154,11 @@
*/
#define FF_FS_RPATH 2
#ifdef FUSEE_STAGE2_SRC
#define FF_FS_RPATH 2
#else
#define FF_FS_RPATH 0
#endif
/* This option configures support for relative path.
/
/ 0: Disable relative path and remove related functions.
@ -163,12 +171,21 @@
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#define FF_VOLUMES 10
#ifdef FUSEE_STAGE2_SRC
#define FF_VOLUMES 10
#else
#define FF_VOLUMES 1
#endif
/* Number of volumes (logical drives) to be used. (1-10) */
#define FF_STR_VOLUME_ID 1
//#define FF_VOLUME_STRS "sdmc"
#ifdef FUSEE_STAGE2_SRC
#define FF_STR_VOLUME_ID 1
//#define FF_VOLUME_STRS "sdmc"
#else
#define FF_STR_VOLUME_ID 0
#define FF_VOLUME_STRS "sdmc"
#endif
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
@ -181,7 +198,7 @@
*/
#define FF_MULTI_PARTITION 0
#define FF_MULTI_PARTITION 0
/* This option switches support for multiple volumes on the physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
@ -190,8 +207,12 @@
/ funciton will be available. */
#define FF_MIN_SS 512
#define FF_MAX_SS 4096
#define FF_MIN_SS 512
#ifdef FUSEE_STAGE2_SRC
#define FF_MAX_SS 4096
#else
#define FF_MAX_SS 512
#endif
/* This set of options configures the range of sector size to be supported. (512,
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
/ harddisk. But a larger value may be required for on-board flash memory and some
@ -200,13 +221,55 @@
/ GET_SECTOR_SIZE command. */
#define FF_USE_TRIM 0
#define FF_LBA64 0
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
#define FF_MIN_GPT 0x100000000
/* Minimum number of sectors to switch GPT format to create partition in f_mkfs and
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
#define FF_USE_TRIM 0
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
#define FF_FS_NOFSINFO 0
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
#define FF_FS_EXFAT 1
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
#define FF_FS_NORTC 1
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2019
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_NOFSINFO 0
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
@ -218,39 +281,7 @@
*/
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
#define FF_FS_EXFAT 1
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
#define FF_FS_NORTC 1
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2018
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_LOCK 0
#define FF_FS_LOCK 0
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
/ is 1.
@ -262,10 +293,10 @@
/ lock control is independent of re-entrancy. */
/* #include <somertos.h> // O/S definitions */
#define FF_FS_REENTRANT 0
#define FF_FS_TIMEOUT 1000
#define FF_SYNC_t HANDLE
/* #include <somertos.h> // O/S definitions */
#define FF_FS_REENTRANT 0
#define FF_FS_TIMEOUT 1000
#define FF_SYNC_t HANDLE
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()

170
fusee/common/fatfs/ffsystem.c Normal file
View file

@ -0,0 +1,170 @@
/*------------------------------------------------------------------------*/
/* Sample Code of OS Dependent Functions for FatFs */
/* (C)ChaN, 2018 */
/*------------------------------------------------------------------------*/
#include "ff.h"
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
/*------------------------------------------------------------------------*/
/* Allocate a memory block */
/*------------------------------------------------------------------------*/
void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */
UINT msize /* Number of bytes to allocate */
)
{
return malloc(msize); /* Allocate a new memory block with POSIX API */
}
/*------------------------------------------------------------------------*/
/* Free a memory block */
/*------------------------------------------------------------------------*/
void ff_memfree (
void* mblock /* Pointer to the memory block to free (nothing to do if null) */
)
{
free(mblock); /* Free the memory block with POSIX API */
}
#endif
#if FF_FS_REENTRANT /* Mutal exclusion */
/*------------------------------------------------------------------------*/
/* Create a Synchronization Object */
/*------------------------------------------------------------------------*/
/* This function is called in f_mount() function to create a new
/ synchronization object for the volume, such as semaphore and mutex.
/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
*/
//const osMutexDef_t Mutex[FF_VOLUMES]; /* Table of CMSIS-RTOS mutex */
int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
BYTE vol, /* Corresponding volume (logical drive number) */
FF_SYNC_t* sobj /* Pointer to return the created sync object */
)
{
/* Win32 */
*sobj = CreateMutex(NULL, FALSE, NULL);
return (int)(*sobj != INVALID_HANDLE_VALUE);
/* uITRON */
// T_CSEM csem = {TA_TPRI,1,1};
// *sobj = acre_sem(&csem);
// return (int)(*sobj > 0);
/* uC/OS-II */
// OS_ERR err;
// *sobj = OSMutexCreate(0, &err);
// return (int)(err == OS_NO_ERR);
/* FreeRTOS */
// *sobj = xSemaphoreCreateMutex();
// return (int)(*sobj != NULL);
/* CMSIS-RTOS */
// *sobj = osMutexCreate(&Mutex[vol]);
// return (int)(*sobj != NULL);
}
/*------------------------------------------------------------------------*/
/* Delete a Synchronization Object */
/*------------------------------------------------------------------------*/
/* This function is called in f_mount() function to delete a synchronization
/ object that created with ff_cre_syncobj() function. When a 0 is returned,
/ the f_mount() function fails with FR_INT_ERR.
*/
int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
)
{
/* Win32 */
return (int)CloseHandle(sobj);
/* uITRON */
// return (int)(del_sem(sobj) == E_OK);
/* uC/OS-II */
// OS_ERR err;
// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
// return (int)(err == OS_NO_ERR);
/* FreeRTOS */
// vSemaphoreDelete(sobj);
// return 1;
/* CMSIS-RTOS */
// return (int)(osMutexDelete(sobj) == osOK);
}
/*------------------------------------------------------------------------*/
/* Request Grant to Access the Volume */
/*------------------------------------------------------------------------*/
/* This function is called on entering file functions to lock the volume.
/ When a 0 is returned, the file function fails with FR_TIMEOUT.
*/
int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
FF_SYNC_t sobj /* Sync object to wait */
)
{
/* Win32 */
return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
/* uITRON */
// return (int)(wai_sem(sobj) == E_OK);
/* uC/OS-II */
// OS_ERR err;
// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
// return (int)(err == OS_NO_ERR);
/* FreeRTOS */
// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
/* CMSIS-RTOS */
// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
}
/*------------------------------------------------------------------------*/
/* Release Grant to Access the Volume */
/*------------------------------------------------------------------------*/
/* This function is called on leaving file functions to unlock the volume.
*/
void ff_rel_grant (
FF_SYNC_t sobj /* Sync object to be signaled */
)
{
/* Win32 */
ReleaseMutex(sobj);
/* uITRON */
// sig_sem(sobj);
/* uC/OS-II */
// OSMutexPost(sobj);
/* FreeRTOS */
// xSemaphoreGive(sobj);
/* CMSIS-RTOS */
// osMutexRelease(sobj);
}
#endif

15593
fusee/common/fatfs/ffunicode.c Normal file
View file

File diff suppressed because it is too large Load diff

0
fusee/fusee-primary/src/lib/ini.c → fusee/common/ini.c
View file

0
fusee/fusee-primary/src/lib/ini.h → fusee/common/ini.h
View file

41
fusee/fusee-secondary/src/lib/log.c → fusee/common/log.c
View file

@ -15,11 +15,16 @@
*/
#include "log.h"
#include "../console.h"
#ifdef FUSEE_STAGE2_SRC
#include "../../../fusee/fusee-secondary/src/console.h"
#include <stdio.h>
#else
#include "display/video_fb.h"
#include "vsprintf.h"
#endif
/* default log level for screen output */
/* Default log level for screen output. */
ScreenLogLevel g_screen_log_level = SCREEN_LOG_LEVEL_NONE;
void log_set_log_level(ScreenLogLevel log_level) {
@ -31,14 +36,18 @@ ScreenLogLevel log_get_log_level() {
}
void log_to_uart(const char *message) {
/* TODO: add UART logging */
/* TODO: Add UART logging. */
}
static void print_to_screen(ScreenLogLevel screen_log_level, char *message) {
/* don't print to screen if below log level */
/* Don't print to screen if below log level */
if(screen_log_level > g_screen_log_level) return;
#ifdef FUSEE_STAGE2_SRC
printf(message);
#else
video_puts(message);
#endif
}
/**
@ -53,10 +62,10 @@ void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args)
char buf[PRINT_MESSAGE_MAX_LENGTH];
vsnprintf(buf, PRINT_MESSAGE_MAX_LENGTH, fmt, args);
/* we don't need that flag here, but if it gets used, strip it so we print correctly */
/* We don't need that flag here, but if it gets used, strip it so we print correctly. */
screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
/* log to UART */
/* Log to UART. */
log_to_uart(buf);
print_to_screen(screen_log_level, buf);
@ -65,8 +74,8 @@ void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args)
static void add_prefix(ScreenLogLevel screen_log_level, const char *fmt, char *buf) {
char typebuf[] = "[%s] %s";
/* apply prefix and append message format */
/* TODO: add coloring to the output */
/* Apply prefix and append message format. */
/* TODO: Add coloring to the output. */
switch(screen_log_level)
{
case SCREEN_LOG_LEVEL_ERROR:
@ -91,7 +100,7 @@ static void add_prefix(ScreenLogLevel screen_log_level, const char *fmt, char *b
/**
* print - logs a message and prints it to screen based on its screen_log_level
*
*
* If the level is below g_screen_log_level it will not be shown but logged to UART
* Use SCREEN_LOG_LEVEL_NO_PREFIX if you don't want a prefix to be added
* UART is TODO
@ -101,14 +110,16 @@ void print(ScreenLogLevel screen_log_level, const char * fmt, ...)
char buf[PRINT_MESSAGE_MAX_LENGTH] = {};
char message[PRINT_MESSAGE_MAX_LENGTH] = {};
/* Make splash disappear if level is ERROR or WARNING */
/* Make splash disappear if level is ERROR or WARNING. */
#ifdef FUSEE_STAGE2_SRC
if (screen_log_level < SCREEN_LOG_LEVEL_MANDATORY) {
console_resume();
}
#endif
/* make prefix free messages with log_level possible */
/* Make prefix free messages with log_level possible. */
if(screen_log_level & SCREEN_LOG_LEVEL_NO_PREFIX) {
/* remove the NO_PREFIX flag so the enum can be recognized later on */
/* Remove the NO_PREFIX flag so the enum can be recognized later on. */
screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
@ -117,13 +128,13 @@ void print(ScreenLogLevel screen_log_level, const char * fmt, ...)
add_prefix(screen_log_level, fmt, buf);
}
/* input arguments */
/* Input arguments. */
va_list args;
va_start(args, fmt);
vsnprintf(message, PRINT_MESSAGE_MAX_LENGTH, buf, args);
va_end(args);
/* log to UART */
/* Log to UART. */
log_to_uart(message);
print_to_screen(screen_log_level, message);

5
fusee/fusee-secondary/src/lib/log.h → fusee/common/log.h
View file

@ -25,11 +25,12 @@ typedef enum {
SCREEN_LOG_LEVEL_NONE = 0,
SCREEN_LOG_LEVEL_ERROR = 1,
SCREEN_LOG_LEVEL_WARNING = 2,
SCREEN_LOG_LEVEL_MANDATORY = 3, /* no log prefix */
SCREEN_LOG_LEVEL_MANDATORY = 3, /* No log prefix. */
SCREEN_LOG_LEVEL_INFO = 4,
SCREEN_LOG_LEVEL_DEBUG = 5,
SCREEN_LOG_LEVEL_SD_DEBUG = 6,
SCREEN_LOG_LEVEL_NO_PREFIX = 0x100 /* OR this to your LOG_LEVEL to prevent prefix creation */
SCREEN_LOG_LEVEL_NO_PREFIX = 0x100 /* OR this to your LOG_LEVEL to prevent prefix creation. */
} ScreenLogLevel;
extern ScreenLogLevel g_screen_log_level;

0
fusee/fusee-primary/src/lib/lz.c → fusee/common/lz.c
View file

0
fusee/fusee-primary/src/lib/lz.h → fusee/common/lz.h
View file

0
fusee/fusee-primary/src/sdmmc/mmc.h → fusee/common/sdmmc/mmc.h
View file

0
fusee/fusee-primary/src/sdmmc/sd.h → fusee/common/sdmmc/sd.h
View file

1047
fusee/fusee-secondary/src/sdmmc/sdmmc.c → fusee/common/sdmmc/sdmmc.c
View file

File diff suppressed because it is too large Load diff

0
fusee/fusee-primary/src/sdmmc/sdmmc.h → fusee/common/sdmmc/sdmmc.h
View file

1214
fusee/fusee-secondary/src/sdmmc/sdmmc_core.c → fusee/common/sdmmc/sdmmc_core.c
View file

File diff suppressed because it is too large Load diff

74
sept/sept-secondary/src/sdmmc/sdmmc_core.h → fusee/common/sdmmc/sdmmc_core.h
View file

@ -103,16 +103,22 @@
#define SDMMC_CLOCK_TAP_SDMMC3 (0x03 << 16)
#define SDMMC_CLOCK_TAP_SDMMC4 (0x00 << 16)
#define SDMMC_CLOCK_TRIM_MASK (0xFF << 24)
#define SDMMC_CLOCK_TRIM_SDMMC1 (0x02 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC2 (0x08 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC1_ERISTA (0x02 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC1_MARIKO (0x0E << 24)
#define SDMMC_CLOCK_TRIM_SDMMC2_ERISTA (0x08 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC2_MARIKO (0x0D << 24)
#define SDMMC_CLOCK_TRIM_SDMMC3 (0x03 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC4 (0x08 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC4_ERISTA (0x08 << 24)
#define SDMMC_CLOCK_TRIM_SDMMC4_MARIKO (0x0D << 24)
#define SDMMC_CLOCK_SPI_MODE_CLKEN_OVERRIDE (1 << 2)
#define SDMMC_CLOCK_PADPIPE_CLKEN_OVERRIDE (1 << 3)
/* Autocal configuration */
#define SDMMC_AUTOCAL_PDPU_CONFIG_MASK 0x7F7F
#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8 0x7B7B
#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3 0x7D00
#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_ERISTA 0x7B7B
#define SDMMC_AUTOCAL_PDPU_SDMMC1_1V8_MARIKO 0x0606
#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_ERISTA 0x7D00
#define SDMMC_AUTOCAL_PDPU_SDMMC1_3V3_MARIKO 0x0000
#define SDMMC_AUTOCAL_PDPU_SDMMC4_1V8 0x0505
#define SDMMC_AUTOCAL_START (1 << 31)
#define SDMMC_AUTOCAL_ENABLE (1 << 29)
@ -190,53 +196,53 @@ typedef enum {
} SdmmcControllerNum;
typedef enum {
SDMMC_PARTITION_INVALID = -1,
SDMMC_PARTITION_USER = 0,
SDMMC_PARTITION_BOOT0 = 1,
SDMMC_PARTITION_BOOT1 = 2,
SDMMC_PARTITION_RPMB = 3
SDMMC_PARTITION_INVALID = -1,
SDMMC_PARTITION_USER = 0,
SDMMC_PARTITION_BOOT0 = 1,
SDMMC_PARTITION_BOOT1 = 2,
SDMMC_PARTITION_RPMB = 3
} SdmmcPartitionNum;
typedef enum {
SDMMC_VOLTAGE_NONE = 0,
SDMMC_VOLTAGE_1V8 = 1,
SDMMC_VOLTAGE_3V3 = 2
SDMMC_VOLTAGE_NONE = 0,
SDMMC_VOLTAGE_1V8 = 1,
SDMMC_VOLTAGE_3V3 = 2
} SdmmcBusVoltage;
typedef enum {
SDMMC_BUS_WIDTH_1BIT = 0,
SDMMC_BUS_WIDTH_4BIT = 1,
SDMMC_BUS_WIDTH_8BIT = 2
SDMMC_BUS_WIDTH_1BIT = 0,
SDMMC_BUS_WIDTH_4BIT = 1,
SDMMC_BUS_WIDTH_8BIT = 2
} SdmmcBusWidth;
typedef enum {
SDMMC_SPEED_MMC_INIT = 0,
SDMMC_SPEED_MMC_IDENT = 0,
SDMMC_SPEED_MMC_LEGACY = 1,
SDMMC_SPEED_MMC_HS = 2,
SDMMC_SPEED_MMC_HS200 = 3,
SDMMC_SPEED_MMC_HS400 = 4,
SDMMC_SPEED_SD_INIT = 5,
SDMMC_SPEED_SD_LEGACY = 6,
SDMMC_SPEED_SD_IDENT = 5,
SDMMC_SPEED_SD_DS = 6,
SDMMC_SPEED_SD_HS = 7,
SDMMC_SPEED_UHS_SDR12 = 8,
SDMMC_SPEED_UHS_SDR25 = 9,
SDMMC_SPEED_UHS_SDR50 = 10,
SDMMC_SPEED_UHS_SDR104 = 11,
SDMMC_SPEED_UHS_RESERVED = 12,
SDMMC_SPEED_UHS_DDR50 = 13,
SDMMC_SPEED_MMC_DDR52 = 14,
SDMMC_SPEED_SD_SDR12 = 8,
SDMMC_SPEED_SD_SDR25 = 9,
SDMMC_SPEED_SD_SDR50 = 10,
SDMMC_SPEED_SD_SDR104 = 11,
SDMMC_SPEED_SD_DDR50 = 12,
SDMMC_SPEED_GC_ASIC_FPGA = 13,
SDMMC_SPEED_GC_ASIC = 14,
SDMMC_SPEED_EMU_SDR104 = 255, /* Custom speed mode. Prevents low voltage switch in MMC emulation. */
} SdmmcBusSpeed;
typedef enum {
SDMMC_CAR_DIVIDER_UHS_SDR12 = 31, /* (16.5 * 2) - 2 */
SDMMC_CAR_DIVIDER_UHS_SDR25 = 15, /* (8.5 * 2) - 2 */
SDMMC_CAR_DIVIDER_UHS_SDR50 = 7, /* (4.5 * 2) - 2 */
SDMMC_CAR_DIVIDER_UHS_SDR104 = 2, /* (2 * 2) - 2 */
SDMMC_CAR_DIVIDER_UHS_DDR50 = 18, /* (5 * 2 * 2) - 2 */
SDMMC_CAR_DIVIDER_MMC_LEGACY = 30, /* (16 * 2) - 2 */
SDMMC_CAR_DIVIDER_MMC_HS = 14, /* (8 * 2) - 2 */
SDMMC_CAR_DIVIDER_MMC_HS200 = 3, /* (2.5 * 2) - 2 (for PLLP_OUT0, same as HS400) */
SDMMC_CAR_DIVIDER_MMC_LEGACY = 30, /* (16 * 2) - 2 */
SDMMC_CAR_DIVIDER_MMC_HS = 14, /* (8 * 2) - 2 */
SDMMC_CAR_DIVIDER_MMC_HS200 = 3, /* (2.5 * 2) - 2 (for PLLP_OUT0, same as HS400) */
SDMMC_CAR_DIVIDER_SD_SDR12 = 31, /* (16.5 * 2) - 2 */
SDMMC_CAR_DIVIDER_SD_SDR25 = 15, /* (8.5 * 2) - 2 */
SDMMC_CAR_DIVIDER_SD_SDR50 = 7, /* (4.5 * 2) - 2 */
SDMMC_CAR_DIVIDER_SD_SDR104 = 2, /* (2 * 2) - 2 */
SDMMC_CAR_DIVIDER_GC_ASIC_FPGA = 18, /* (5 * 2 * 2) - 2 */
} SdmmcCarDivider;
/* Structure for describing a SDMMC device. */

0
fusee/fusee-primary/src/sdmmc/sdmmc_tegra.h → fusee/common/sdmmc/sdmmc_tegra.h
View file

0
fusee/fusee-mtc/src/lib/vsprintf.c → fusee/common/vsprintf.c
View file

0
fusee/fusee-mtc/src/lib/vsprintf.h → fusee/common/vsprintf.h
View file

4
fusee/fusee-mtc/Makefile
View file

@ -27,7 +27,7 @@ endif
#---------------------------------------------------------------------------------
TARGET := $(notdir $(CURDIR))
BUILD := build
SOURCES := src src/lib src/display
SOURCES := src ../../fusee/common ../../fusee/common/display
DATA := data
INCLUDES := include ../../libraries/libvapours/include
@ -35,7 +35,7 @@ INCLUDES := include ../../libraries/libvapours/include
# options for code generation
#---------------------------------------------------------------------------------
ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
DEFINES := -D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
DEFINES := -D__BPMP__ -DFUSEE_MTC_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
CFLAGS := \
-g \

3
fusee/fusee-mtc/src/car.c
View file

@ -35,6 +35,7 @@ static inline uint32_t get_clk_source_reg(CarDevice dev) {
case CARDEVICE_KFUSE: return 0;
case CARDEVICE_CL_DVFS: return 0;
case CARDEVICE_CORESIGHT: return 0x1D4;
case CARDEVICE_MSELECT: return 0x3B4;
case CARDEVICE_ACTMON: return 0x3E8;
case CARDEVICE_BPMP: return 0;
default: generic_panic();
@ -58,6 +59,7 @@ static inline uint32_t get_clk_source_val(CarDevice dev) {
case CARDEVICE_KFUSE: return 0;
case CARDEVICE_CL_DVFS: return 0;
case CARDEVICE_CORESIGHT: return 0;
case CARDEVICE_MSELECT: return 0;
case CARDEVICE_ACTMON: return 6;
case CARDEVICE_BPMP: return 0;
default: generic_panic();
@ -81,6 +83,7 @@ static inline uint32_t get_clk_source_div(CarDevice dev) {
case CARDEVICE_KFUSE: return 0;
case CARDEVICE_CL_DVFS: return 0;
case CARDEVICE_CORESIGHT: return 4;
case CARDEVICE_MSELECT: return 6;
case CARDEVICE_ACTMON: return 0;
case CARDEVICE_BPMP: return 0;
default: generic_panic();

75
fusee/fusee-mtc/src/car.h
View file

@ -37,23 +37,28 @@
/* Clock and reset devices. */
typedef enum {
CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_BPMP = ((0 << 5) | 0x1),
CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_USBD = ((0 << 5) | 0x16),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
CARDEVICE_APBDMA = ((1 << 5) | 0x2),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_BPMP = ((0 << 5) | 0x1)
CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_MSELECT = ((3 << 5) | 0x8),
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
} CarDevice;
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -97,31 +102,31 @@ typedef struct {
uint32_t pllc_out;
uint32_t pllc_misc0;
uint32_t pllc_misc1;
/* PLLM 0x90-0x9c */
uint32_t pllm_base;
uint32_t pllm_out;
uint32_t pllm_misc1;
uint32_t pllm_misc2;
/* PLLP 0xa0-0xac */
uint32_t pllp_base;
uint32_t pllp_outa;
uint32_t pllp_outb;
uint32_t pllp_misc;
/* PLLA 0xb0-0xbc */
uint32_t plla_base;
uint32_t plla_out;
uint32_t plla_misc0;
uint32_t plla_misc1;
/* PLLU 0xc0-0xcc */
uint32_t pllu_base;
uint32_t pllu_out;
uint32_t pllu_misc1;
uint32_t pllu_misc2;
/* PLLD 0xd0-0xdc */
uint32_t plld_base;
uint32_t plld_out;
@ -131,13 +136,13 @@ typedef struct {
/* PLLX 0xe0-0xe4 */
uint32_t pllx_base;
uint32_t pllx_misc;
/* PLLE 0xe8-0xf4 */
uint32_t plle_base;
uint32_t plle_misc;
uint32_t plle_ss_cntl1;
uint32_t plle_ss_cntl2;
uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */
uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */
@ -188,7 +193,7 @@ typedef struct {
uint32_t _0x1e0[5];
uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */
uint32_t _0x1f8;
uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */
uint32_t _0x200[32];
@ -257,7 +262,7 @@ typedef struct {
uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */
uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */
uint32_t _0x3a8[2];
uint32_t _0x3b0;
uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */
uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */
@ -283,7 +288,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c;
uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set;
@ -371,13 +376,13 @@ typedef struct {
uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */
uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
uint32_t _0x568[2];
uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */
uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */
uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */
uint32_t _0x57c[5];
uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/
uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */
uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
@ -399,7 +404,7 @@ typedef struct {
uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */
uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */
uint32_t _0x5f8[2];
uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */
uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */
uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */
@ -428,7 +433,7 @@ typedef struct {
uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */
uint32_t _0x670[2];
uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */
uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */
uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */
uint32_t _0x684[2];
@ -439,14 +444,14 @@ typedef struct {
uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */
uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */
uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */
uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */
uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */
uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */
uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */
uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */
uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */
uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */
uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */
@ -455,11 +460,11 @@ typedef struct {
uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */
uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */
uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */
uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */
uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */
uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
@ -470,7 +475,7 @@ typedef struct {
uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */
uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */
uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */

57
fusee/fusee-mtc/src/display/video_fb.h
View file

@ -1,57 +0,0 @@
/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VIDEO_FB_H_
#define _VIDEO_FB_H_
#define CONSOLE_BG_COL 0x00
#define CONSOLE_FG_COL 0xa0
/* Try using the small font */
#define CONFIG_VIDEO_FONT_SMALL
/*
* Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
*/
#define GDF__8BIT_INDEX 0
#define GDF_15BIT_555RGB 1
#define GDF_16BIT_565RGB 2
#define GDF_32BIT_X888RGB 3
#define GDF_24BIT_888RGB 4
#define GDF__8BIT_332RGB 5
#define CONFIG_VIDEO_FB_LITTLE_ENDIAN
#define CONFIG_VIDEO_VISIBLE_COLS 720
#define CONFIG_VIDEO_VISIBLE_ROWS 1280
#define CONFIG_VIDEO_COLS 768
#define CONFIG_VIDEO_PIXEL_SIZE 4
#define CONFIG_VIDEO_DATA_FORMAT GDF_32BIT_X888RGB /* BGR actually, but w/e */
int video_get_col(void);
int video_get_row(void);
int video_init(void *fb);
int video_resume(void *fb, int row, int col);
void video_puts(const char *s);
#endif /*_VIDEO_FB_H_ */

40
fusee/fusee-mtc/src/emc.h
View file

@ -1086,4 +1086,44 @@
#define EMC_PMC_SCRATCH2 0x444
#define EMC_PMC_SCRATCH3 0x448
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 0xd40
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 0xd44
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 0xd48
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 0xd4c
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 0xd50
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 0xd54
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 0xd60
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 0xd64
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 0xd68
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 0xd6c
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 0xd70
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 0xd74
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 0xd80
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 0xd84
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 0xd88
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 0xd8c
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 0xd90
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 0xd94
#define EMC_PMACRO_PMU_OUT_EOFF1_0 0xda0
#define EMC_PMACRO_PMU_OUT_EOFF1_1 0xda4
#define EMC_PMACRO_PMU_OUT_EOFF1_2 0xda8
#define EMC_PMACRO_PMU_OUT_EOFF1_3 0xdac
#define EMC_PMACRO_PMU_OUT_EOFF1_4 0xdb0
#define EMC_PMACRO_PMU_OUT_EOFF1_5 0xdb4
#define EMC_PMACRO_COMP_PMU_OUT 0xdc0
#define EMC_PMACRO_DATA_PI_CTRL 0x110
#define EMC_PMACRO_CMD_PI_CTRL 0x114
#define EMC_AUTO_CAL_CONFIG9 0x42c
#define EMC_TRTM 0xbc
#define EMC_TWTM 0xf8
#define EMC_TRATM 0xfc
#define EMC_TWATM 0x108
#define EMC_TR2REF 0x10c
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 0xc6c
#endif

199
fusee/fusee-mtc/src/fuse.c
View file

@ -24,11 +24,6 @@
#include "pmc.h"
#include "timers.h"
/* Prototypes for internal commands. */
void fuse_enable_power(void);
void fuse_disable_power(void);
void fuse_wait_idle(void);
/* Initialize the fuse driver */
void fuse_init(void) {
/* Make all fuse registers visible, disable the private key and disable programming. */
@ -43,7 +38,7 @@ void fuse_disable_private_key(void) {
fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
}
/* Disables all fuse programming. */
/* Disable all fuse programming. */
void fuse_disable_programming(void) {
volatile tegra_fuse_t *fuse = fuse_get_regs();
fuse->FUSE_DISABLEREGPROGRAM = 1;
@ -68,13 +63,14 @@ void fuse_disable_power(void) {
}
/* Wait for the fuse driver to go idle. */
void fuse_wait_idle(void) {
static void fuse_wait_idle(void) {
volatile tegra_fuse_t *fuse = fuse_get_regs();
uint32_t ctrl_val = 0;
/* Wait for STATE_IDLE */
while ((ctrl_val & (0xF0000)) != 0x40000)
while ((ctrl_val & (0xF0000)) != 0x40000) {
ctrl_val = fuse->FUSE_FUSECTRL;
}
}
/* Read a fuse from the hardware array. */
@ -120,7 +116,7 @@ void fuse_hw_write(uint32_t value, uint32_t addr) {
fuse_wait_idle();
}
/* Sense the fuse hardware array into the shadow cache. */
/* Sense the fuse hardware array into the fuse cache. */
void fuse_hw_sense(void) {
volatile tegra_fuse_t *fuse = fuse_get_regs();
@ -137,46 +133,68 @@ void fuse_hw_sense(void) {
fuse_wait_idle();
}
/* Read the SKU info register from the shadow cache. */
/* Read the SKU info register. */
uint32_t fuse_get_sku_info(void) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
return fuse_chip->FUSE_SKU_INFO;
}
/* Read the bootrom patch version from a register in the shadow cache. */
/* Read the bootrom patch version. */
uint32_t fuse_get_bootrom_patch_version(void) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
}
/* Read a spare bit register from the shadow cache */
uint32_t fuse_get_spare_bit(uint32_t idx) {
if (idx < 32) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
return fuse_chip->FUSE_SPARE_BIT[idx];
} else {
return 0;
/* Read a spare bit register. */
uint32_t fuse_get_spare_bit(uint32_t index) {
uint32_t soc_type = fuse_get_soc_type();
if (soc_type == 0) {
if (index < 32) {
volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
return fuse_chip->FUSE_SPARE_BIT[index];
}
} else if (soc_type == 1) {
if (index < 30) {
volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
return fuse_chip->FUSE_SPARE_BIT[index];
}
}
return 0;
}
/* Read a reserved ODM register from the shadow cache. */
uint32_t fuse_get_reserved_odm(uint32_t idx) {
if (idx < 8) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
return fuse_chip->FUSE_RESERVED_ODM[idx];
/* Read a reserved ODM register. */
uint32_t fuse_get_reserved_odm(uint32_t index) {
if (index < 8) {
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
return fuse_chip->FUSE_RESERVED_ODM0[index];
} else {
return 0;
uint32_t soc_type = fuse_get_soc_type();
if (soc_type == 1) {
volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
if (index < 22) {
return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
} else if (index < 25) {
return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
} else if (index < 26) {
return fuse_chip->FUSE_RESERVED_ODM25;
} else if (index < 29) {
return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
} else if (index < 30) {
return fuse_chip->FUSE_RESERVED_ODM29;
}
}
}
return 0;
}
/* Get the DRAM ID using values in the shadow cache. */
/* Get the DramId. */
uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7);
return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
}
/* Derive the Device ID using values in the shadow cache. */
/* Derive the DeviceId. */
uint64_t fuse_get_device_id(void) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
uint64_t device_id = 0;
uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
@ -200,48 +218,74 @@ uint64_t fuse_get_device_id(void) {
return device_id;
}
/* Derive the Hardware Type using values in the shadow cache. */
uint32_t fuse_get_hardware_type(uint32_t target_firmware) {
/* Derive the HardwareType with firmware specific checks. */
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
/* Firmware from versions 1.0.0 to 3.0.2. */
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
if (hardware_type >= 1) {
return (hardware_type > 2) ? 3 : hardware_type - 1;
} else if ((fuse_chip->FUSE_SPARE_BIT[9] & 1) == 0) {
return 0;
} else {
return 3;
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
switch (hardware_type) {
case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 1; /* HardwareType_Copper */
default: return 3; /* HardwareType_Undefined */
}
} else if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { /* Firmware versions from 4.0.0 to 6.2.0. */
static const uint32_t types[] = {0,1,4,3};
} else {
hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
hardware_type--;
return (hardware_type > 3) ? 4 : types[hardware_type];
} else { /* Firmware versions from 7.0.0 onwards. */
/* Always return 0 in retail. */
return 0;
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
switch (hardware_type) {
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 1; /* HardwareType_Copper */
case 0x04: return 3; /* HardwareType_Iowa */
default: return 4; /* HardwareType_Undefined */
}
} else {
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
switch (hardware_type) {
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 4; /* HardwareType_Calcio */
case 0x04: return 3; /* HardwareType_Iowa */
case 0x08: return 2; /* HardwareType_Hoag */
default: return 0xF; /* HardwareType_Undefined */
}
} else {
switch (hardware_type) {
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 4; /* HardwareType_Calcio */
case 0x04: return 3; /* HardwareType_Iowa */
case 0x08: return 2; /* HardwareType_Hoag */
case 0x10: return 5; /* HardwareType_Five */
default: return 0xF; /* HardwareType_Undefined */
}
}
}
}
}
/* Derive the Retail Type using values in the shadow cache. */
uint32_t fuse_get_retail_type(void) {
/* Retail Type = IS_RETAIL | UNIT_TYPE. */
/* Derive the HardwareType. */
uint32_t fuse_get_hardware_type(void) {
return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
}
/* Derive the HardwareState. */
uint32_t fuse_get_hardware_state(void) {
uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
uint32_t retail_type = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */
return 1;
} else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */
return 0;
uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
switch (hardware_state) {
case 0x03: return 0; /* HardwareState_Development */
case 0x04: return 1; /* HardwareState_Production */
default: return 2; /* HardwareState_Undefined */
}
return 2; /* IS_RETAIL | DEV_UNIT */
}
/* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */
/* Derive the 16-byte HardwareInfo and copy to output buffer. */
void fuse_get_hardware_info(void *dst) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
uint32_t hw_info[0x4];
uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
@ -261,3 +305,42 @@ void fuse_get_hardware_info(void *dst) {
memcpy(dst, hw_info, 0x10);
}
/* Check if have a new ODM fuse format. */
bool fuse_is_new_format(void) {
return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
}
/* Get the DeviceUniqueKeyGeneration. */
uint32_t fuse_get_device_unique_key_generation(void) {
if (fuse_is_new_format()) {
return (fuse_get_reserved_odm(2) & 0x1F);
} else {
return 0;
}
}
/* Get the SocType from the HardwareType. */
uint32_t fuse_get_soc_type(void) {
switch (fuse_get_hardware_type()) {
case 0:
case 1:
return 0; /* SocType_Erista */
case 3:
case 2:
case 4:
case 5:
return 1; /* SocType_Mariko */
default:
return 0xF; /* SocType_Undefined */
}
}
/* Get the Regulator type. */
uint32_t fuse_get_regulator(void) {
if (fuse_get_soc_type() == 1) {
return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
} else {
return 0; /* Regulator_Erista_Max77621 */
}
}

359
fusee/fusee-mtc/src/fuse.h
View file

@ -18,7 +18,7 @@
#define FUSEE_FUSE_H
#define FUSE_BASE 0x7000F800
#define FUSE_CHIP_BASE (FUSE_BASE + 0x100)
#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
@ -47,10 +47,11 @@ typedef struct {
uint32_t FUSE_PRIVATE_KEY2_NONZERO;
uint32_t FUSE_PRIVATE_KEY3_NONZERO;
uint32_t FUSE_PRIVATE_KEY4_NONZERO;
uint32_t _0x90[0x1C];
uint32_t _0x94;
} tegra_fuse_t;
typedef struct {
uint32_t _0x98[0x1A];
uint32_t FUSE_PRODUCTION_MODE;
uint32_t FUSE_JTAG_SECUREID_VALID;
uint32_t FUSE_ODM_LOCK;
@ -58,9 +59,7 @@ typedef struct {
uint32_t FUSE_SKU_INFO;
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
uint32_t FUSE_CPU_IDDQ_CALIB;
uint32_t FUSE_DAC_CRT_CALIB;
uint32_t FUSE_DAC_HDTV_CALIB;
uint32_t FUSE_DAC_SDTV_CALIB;
uint32_t _0x11C[0x3];
uint32_t FUSE_OPT_FT_REV;
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
@ -68,7 +67,7 @@ typedef struct {
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_IDDQ_CALIB;
uint32_t FUSE_RESERVED_PRODUCTION_WP;
uint32_t _0x144;
uint32_t FUSE_FA;
uint32_t FUSE_RESERVED_PRODUCTION;
uint32_t FUSE_HDMI_LANE0_CALIB;
@ -79,7 +78,7 @@ typedef struct {
uint32_t FUSE_PUBLIC_KEY[0x8];
uint32_t FUSE_TSENSOR1_CALIB;
uint32_t FUSE_TSENSOR2_CALIB;
uint32_t FUSE_VSENSOR_CALIB;
uint32_t _0x18C;
uint32_t FUSE_OPT_CP_REV;
uint32_t FUSE_OPT_PFG;
uint32_t FUSE_TSENSOR0_CALIB;
@ -90,9 +89,9 @@ typedef struct {
uint32_t FUSE_BOOT_DEVICE_INFO;
uint32_t FUSE_RESERVED_SW;
uint32_t FUSE_OPT_VP9_DISABLE;
uint32_t FUSE_RESERVED_ODM[0x8];
uint32_t FUSE_RESERVED_ODM0[0x8];
uint32_t FUSE_OBS_DIS;
uint32_t FUSE_NOR_INFO;
uint32_t _0x1EC;
uint32_t FUSE_USB_CALIB;
uint32_t FUSE_SKU_DIRECT_CONFIG;
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
@ -106,14 +105,12 @@ typedef struct {
uint32_t FUSE_OPT_Y_COORDINATE;
uint32_t FUSE_OPT_SEC_DEBUG_EN;
uint32_t FUSE_OPT_OPS_RESERVED;
uint32_t FUSE_SATA_CALIB;
uint32_t _0x224;
uint32_t FUSE_GPU_IDDQ_CALIB;
uint32_t FUSE_TSENSOR3_CALIB;
uint32_t FUSE_SKU_BOND_OUT_L;
uint32_t FUSE_SKU_BOND_OUT_H;
uint32_t FUSE_SKU_BOND_OUT_U;
uint32_t FUSE_SKU_BOND_OUT_V;
uint32_t FUSE_SKU_BOND_OUT_W;
uint32_t FUSE_CLOCK_BOUNDOUT0;
uint32_t FUSE_CLOCK_BOUNDOUT1;
uint32_t _0x238[0x3];
uint32_t FUSE_OPT_SAMPLE_TYPE;
uint32_t FUSE_OPT_SUBREVISION;
uint32_t FUSE_OPT_SW_RESERVED_0;
@ -123,35 +120,26 @@ typedef struct {
uint32_t FUSE_TSENSOR6_CALIB;
uint32_t FUSE_TSENSOR7_CALIB;
uint32_t FUSE_OPT_PRIV_SEC_EN;
uint32_t FUSE_PKC_DISABLE;
uint32_t _0x16C;
uint32_t _0x170;
uint32_t _0x174;
uint32_t _0x178;
uint32_t _0x268[0x5];
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
uint32_t FUSE_TSENSOR_COMMON;
uint32_t FUSE_OPT_CP_BIN;
uint32_t FUSE_OPT_GPU_DISABLE;
uint32_t FUSE_OPT_FT_BIN;
uint32_t FUSE_OPT_DONE_MAP;
uint32_t _0x194;
uint32_t _0x294;
uint32_t FUSE_APB2JTAG_DISABLE;
uint32_t FUSE_ODM_INFO;
uint32_t _0x1A0;
uint32_t _0x1A4;
uint32_t _0x2A0[0x2];
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
uint32_t _0x1AC;
uint32_t _0x1B0;
uint32_t _0x1B4;
uint32_t _0x1B8;
uint32_t _0x1BC;
uint32_t _0x2AC[0x5];
uint32_t FUSE_WOA_SKU_FLAG;
uint32_t FUSE_ECO_RESERVE_1;
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
uint32_t FUSE_PRODUCTION_MONTH;
uint32_t FUSE_RAM_REPAIR_INDICATOR;
uint32_t FUSE_TSENSOR9_CALIB;
uint32_t _0x1D8;
uint32_t _0x2D8;
uint32_t FUSE_VMIN_CALIBRATION;
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
uint32_t FUSE_DEBUG_AUTHENTICATION;
@ -160,8 +148,7 @@ typedef struct {
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
uint32_t FUSE_SPARE_ENDIS;
uint32_t FUSE_ECO_RESERVE_0;
uint32_t _0x1FC;
uint32_t _0x200;
uint32_t _0x2FC[0x2];
uint32_t FUSE_RESERVED_CALIB0;
uint32_t FUSE_RESERVED_CALIB1;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
@ -170,11 +157,7 @@ typedef struct {
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
uint32_t FUSE_TSENSOR10_CALIB;
uint32_t FUSE_TSENSOR10_CALIB_AUX;
uint32_t FUSE_OPT_RAM_SVOP_DP;
uint32_t FUSE_OPT_RAM_SVOP_PDP;
uint32_t FUSE_OPT_RAM_SVOP_REG;
uint32_t FUSE_OPT_RAM_SVOP_SP;
uint32_t FUSE_OPT_RAM_SVOP_SMPDP;
uint32_t _0x324[0x5];
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
@ -183,42 +166,316 @@ typedef struct {
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
uint32_t FUSE_USB_CALIB_EXT;
uint32_t FUSE_RESERVED_FIELD;
uint32_t FUSE_OPT_ECC_EN;
uint32_t _0x25C;
uint32_t _0x260;
uint32_t _0x264;
uint32_t _0x268;
uint32_t _0x26C;
uint32_t _0x270;
uint32_t _0x274;
uint32_t _0x278;
uint32_t _0x358[0x9];
uint32_t FUSE_SPARE_REALIGNMENT_REG;
uint32_t FUSE_SPARE_BIT[0x20];
} tegra_fuse_chip_t;
} tegra_fuse_chip_common_t;
typedef struct {
uint32_t _0x98[0x1A];
uint32_t FUSE_PRODUCTION_MODE;
uint32_t FUSE_JTAG_SECUREID_VALID;
uint32_t FUSE_ODM_LOCK;
uint32_t FUSE_OPT_OPENGL_EN;
uint32_t FUSE_SKU_INFO;
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
uint32_t FUSE_CPU_IDDQ_CALIB;
uint32_t _0x11C[0x3];
uint32_t FUSE_OPT_FT_REV;
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_IDDQ_CALIB;
uint32_t _0x144;
uint32_t FUSE_FA;
uint32_t FUSE_RESERVED_PRODUCTION;
uint32_t FUSE_HDMI_LANE0_CALIB;
uint32_t FUSE_HDMI_LANE1_CALIB;
uint32_t FUSE_HDMI_LANE2_CALIB;
uint32_t FUSE_HDMI_LANE3_CALIB;
uint32_t FUSE_ENCRYPTION_RATE;
uint32_t FUSE_PUBLIC_KEY[0x8];
uint32_t FUSE_TSENSOR1_CALIB;
uint32_t FUSE_TSENSOR2_CALIB;
uint32_t _0x18C;
uint32_t FUSE_OPT_CP_REV;
uint32_t FUSE_OPT_PFG;
uint32_t FUSE_TSENSOR0_CALIB;
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
uint32_t FUSE_SECURITY_MODE;
uint32_t FUSE_PRIVATE_KEY[0x5];
uint32_t FUSE_ARM_JTAG_DIS;
uint32_t FUSE_BOOT_DEVICE_INFO;
uint32_t FUSE_RESERVED_SW;
uint32_t FUSE_OPT_VP9_DISABLE;
uint32_t FUSE_RESERVED_ODM0[0x8];
uint32_t FUSE_OBS_DIS;
uint32_t _0x1EC;
uint32_t FUSE_USB_CALIB;
uint32_t FUSE_SKU_DIRECT_CONFIG;
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
uint32_t FUSE_PACKAGE_INFO;
uint32_t FUSE_OPT_VENDOR_CODE;
uint32_t FUSE_OPT_FAB_CODE;
uint32_t FUSE_OPT_LOT_CODE_0;
uint32_t FUSE_OPT_LOT_CODE_1;
uint32_t FUSE_OPT_WAFER_ID;
uint32_t FUSE_OPT_X_COORDINATE;
uint32_t FUSE_OPT_Y_COORDINATE;
uint32_t FUSE_OPT_SEC_DEBUG_EN;
uint32_t FUSE_OPT_OPS_RESERVED;
uint32_t FUSE_SATA_CALIB; /* Erista only. */
uint32_t FUSE_GPU_IDDQ_CALIB;
uint32_t FUSE_TSENSOR3_CALIB;
uint32_t FUSE_CLOCK_BOUNDOUT0;
uint32_t FUSE_CLOCK_BOUNDOUT1;
uint32_t _0x238[0x3];
uint32_t FUSE_OPT_SAMPLE_TYPE;
uint32_t FUSE_OPT_SUBREVISION;
uint32_t FUSE_OPT_SW_RESERVED_0;
uint32_t FUSE_OPT_SW_RESERVED_1;
uint32_t FUSE_TSENSOR4_CALIB;
uint32_t FUSE_TSENSOR5_CALIB;
uint32_t FUSE_TSENSOR6_CALIB;
uint32_t FUSE_TSENSOR7_CALIB;
uint32_t FUSE_OPT_PRIV_SEC_EN;
uint32_t FUSE_PKC_DISABLE; /* Erista only. */
uint32_t _0x26C[0x4];
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
uint32_t FUSE_TSENSOR_COMMON;
uint32_t FUSE_OPT_CP_BIN;
uint32_t FUSE_OPT_GPU_DISABLE;
uint32_t FUSE_OPT_FT_BIN;
uint32_t FUSE_OPT_DONE_MAP;
uint32_t _0x294;
uint32_t FUSE_APB2JTAG_DISABLE;
uint32_t FUSE_ODM_INFO;
uint32_t _0x2A0[0x2];
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
uint32_t _0x2AC[0x5];
uint32_t FUSE_WOA_SKU_FLAG;
uint32_t FUSE_ECO_RESERVE_1;
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
uint32_t FUSE_PRODUCTION_MONTH;
uint32_t FUSE_RAM_REPAIR_INDICATOR;
uint32_t FUSE_TSENSOR9_CALIB;
uint32_t _0x2D8;
uint32_t FUSE_VMIN_CALIBRATION;
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
uint32_t FUSE_DEBUG_AUTHENTICATION;
uint32_t FUSE_SECURE_PROVISION_INDEX;
uint32_t FUSE_SECURE_PROVISION_INFO;
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
uint32_t FUSE_SPARE_ENDIS;
uint32_t FUSE_ECO_RESERVE_0;
uint32_t _0x2FC[0x2];
uint32_t FUSE_RESERVED_CALIB0;
uint32_t FUSE_RESERVED_CALIB1;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
uint32_t FUSE_OPT_CPU_DISABLE;
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
uint32_t FUSE_TSENSOR10_CALIB;
uint32_t FUSE_TSENSOR10_CALIB_AUX;
uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
uint32_t FUSE_USB_CALIB_EXT;
uint32_t FUSE_RESERVED_FIELD;
uint32_t _0x358[0x9];
uint32_t FUSE_SPARE_REALIGNMENT_REG;
uint32_t FUSE_SPARE_BIT[0x20];
} tegra_fuse_chip_erista_t;
typedef struct {
uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */
uint32_t FUSE_KEK[0x4]; /* Mariko only. */
uint32_t FUSE_BEK[0x4]; /* Mariko only. */
uint32_t _0xF0; /* Mariko only. */
uint32_t _0xF4; /* Mariko only. */
uint32_t _0xF8; /* Mariko only. */
uint32_t _0xFC; /* Mariko only. */
uint32_t FUSE_PRODUCTION_MODE;
uint32_t FUSE_JTAG_SECUREID_VALID;
uint32_t FUSE_ODM_LOCK;
uint32_t FUSE_OPT_OPENGL_EN;
uint32_t FUSE_SKU_INFO;
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
uint32_t FUSE_CPU_IDDQ_CALIB;
uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */
uint32_t FUSE_OPT_FT_REV;
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_IDDQ_CALIB;
uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */
uint32_t FUSE_FA;
uint32_t FUSE_RESERVED_PRODUCTION;
uint32_t FUSE_HDMI_LANE0_CALIB;
uint32_t FUSE_HDMI_LANE1_CALIB;
uint32_t FUSE_HDMI_LANE2_CALIB;
uint32_t FUSE_HDMI_LANE3_CALIB;
uint32_t FUSE_ENCRYPTION_RATE;
uint32_t FUSE_PUBLIC_KEY[0x8];
uint32_t FUSE_TSENSOR1_CALIB;
uint32_t FUSE_TSENSOR2_CALIB;
uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */
uint32_t FUSE_OPT_CP_REV;
uint32_t FUSE_OPT_PFG;
uint32_t FUSE_TSENSOR0_CALIB;
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
uint32_t FUSE_SECURITY_MODE;
uint32_t FUSE_PRIVATE_KEY[0x5];
uint32_t FUSE_ARM_JTAG_DIS;
uint32_t FUSE_BOOT_DEVICE_INFO;
uint32_t FUSE_RESERVED_SW;
uint32_t FUSE_OPT_VP9_DISABLE;
uint32_t FUSE_RESERVED_ODM0[0x8];
uint32_t FUSE_OBS_DIS;
uint32_t _0x1EC; /* Mariko only. */
uint32_t FUSE_USB_CALIB;
uint32_t FUSE_SKU_DIRECT_CONFIG;
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
uint32_t FUSE_PACKAGE_INFO;
uint32_t FUSE_OPT_VENDOR_CODE;
uint32_t FUSE_OPT_FAB_CODE;
uint32_t FUSE_OPT_LOT_CODE_0;
uint32_t FUSE_OPT_LOT_CODE_1;
uint32_t FUSE_OPT_WAFER_ID;
uint32_t FUSE_OPT_X_COORDINATE;
uint32_t FUSE_OPT_Y_COORDINATE;
uint32_t FUSE_OPT_SEC_DEBUG_EN;
uint32_t FUSE_OPT_OPS_RESERVED;
uint32_t _0x224; /* Mariko only. */
uint32_t FUSE_GPU_IDDQ_CALIB;
uint32_t FUSE_TSENSOR3_CALIB;
uint32_t FUSE_CLOCK_BOUNDOUT0;
uint32_t FUSE_CLOCK_BOUNDOUT1;
uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */
uint32_t FUSE_OPT_SAMPLE_TYPE;
uint32_t FUSE_OPT_SUBREVISION;
uint32_t FUSE_OPT_SW_RESERVED_0;
uint32_t FUSE_OPT_SW_RESERVED_1;
uint32_t FUSE_TSENSOR4_CALIB;
uint32_t FUSE_TSENSOR5_CALIB;
uint32_t FUSE_TSENSOR6_CALIB;
uint32_t FUSE_TSENSOR7_CALIB;
uint32_t FUSE_OPT_PRIV_SEC_EN;
uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */
uint32_t _0x26C; /* Mariko only. */
uint32_t _0x270; /* Mariko only. */
uint32_t _0x274; /* Mariko only. */
uint32_t _0x278; /* Mariko only. */
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
uint32_t FUSE_TSENSOR_COMMON;
uint32_t FUSE_OPT_CP_BIN;
uint32_t FUSE_OPT_GPU_DISABLE;
uint32_t FUSE_OPT_FT_BIN;
uint32_t FUSE_OPT_DONE_MAP;
uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */
uint32_t FUSE_APB2JTAG_DISABLE;
uint32_t FUSE_ODM_INFO;
uint32_t _0x2A0[0x2];
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
uint32_t _0x2AC;
uint32_t _0x2B0; /* Mariko only. */
uint32_t _0x2B4; /* Mariko only. */
uint32_t _0x2B8; /* Mariko only. */
uint32_t _0x2BC; /* Mariko only. */
uint32_t FUSE_WOA_SKU_FLAG;
uint32_t FUSE_ECO_RESERVE_1;
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
uint32_t FUSE_PRODUCTION_MONTH;
uint32_t FUSE_RAM_REPAIR_INDICATOR;
uint32_t FUSE_TSENSOR9_CALIB;
uint32_t _0x2D8;
uint32_t FUSE_VMIN_CALIBRATION;
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
uint32_t FUSE_DEBUG_AUTHENTICATION;
uint32_t FUSE_SECURE_PROVISION_INDEX;
uint32_t FUSE_SECURE_PROVISION_INFO;
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
uint32_t FUSE_SPARE_ENDIS;
uint32_t FUSE_ECO_RESERVE_0;
uint32_t _0x2FC[0x2];
uint32_t FUSE_RESERVED_CALIB0;
uint32_t FUSE_RESERVED_CALIB1;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
uint32_t FUSE_OPT_CPU_DISABLE;
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
uint32_t FUSE_TSENSOR10_CALIB;
uint32_t FUSE_TSENSOR10_CALIB_AUX;
uint32_t _0x324; /* Mariko only. */
uint32_t _0x328; /* Mariko only. */
uint32_t _0x32C; /* Mariko only. */
uint32_t _0x330; /* Mariko only. */
uint32_t _0x334; /* Mariko only. */
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
uint32_t FUSE_USB_CALIB_EXT;
uint32_t FUSE_RESERVED_FIELD;
uint32_t _0x358[0x9];
uint32_t FUSE_SPARE_REALIGNMENT_REG;
uint32_t FUSE_SPARE_BIT[0x1E];
} tegra_fuse_chip_mariko_t;
static inline volatile tegra_fuse_t *fuse_get_regs(void)
{
return (volatile tegra_fuse_t *)FUSE_BASE;
}
static inline volatile tegra_fuse_chip_t *fuse_chip_get_regs(void)
static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
{
return (volatile tegra_fuse_chip_t *)FUSE_CHIP_BASE;
return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
}
static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
{
return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
}
static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
{
return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
}
void fuse_init(void);
void fuse_disable_programming(void);
void fuse_disable_private_key(void);
void fuse_enable_power(void);
void fuse_disable_power(void);
uint32_t fuse_get_sku_info(void);
uint32_t fuse_get_spare_bit(uint32_t idx);
uint32_t fuse_get_reserved_odm(uint32_t idx);
uint32_t fuse_get_spare_bit(uint32_t index);
uint32_t fuse_get_reserved_odm(uint32_t index);
uint32_t fuse_get_bootrom_patch_version(void);
uint64_t fuse_get_device_id(void);
uint32_t fuse_get_dram_id(void);
uint32_t fuse_get_hardware_type(uint32_t target_firmware);
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
uint32_t fuse_get_hardware_type(void);
uint32_t fuse_get_retail_type(void);
void fuse_get_hardware_info(void *dst);
bool fuse_is_new_format(void);
uint32_t fuse_get_device_unique_key_generation(void);
uint32_t fuse_get_soc_type(void);
uint32_t fuse_get_regulator(void);
uint32_t fuse_hw_read(uint32_t addr);
void fuse_hw_write(uint32_t value, uint32_t addr);

127
fusee/fusee-mtc/src/lib/log.c
View file

@ -1,127 +0,0 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "log.h"
#include "../display/video_fb.h"
#include "vsprintf.h"
/* default log level for screen output */
ScreenLogLevel g_screen_log_level = SCREEN_LOG_LEVEL_NONE;
void log_set_log_level(ScreenLogLevel log_level) {
g_screen_log_level = log_level;
}
ScreenLogLevel log_get_log_level() {
return g_screen_log_level;
}
void log_to_uart(const char *message) {
/* TODO: add UART logging */
}
static void print_to_screen(ScreenLogLevel screen_log_level, char *message) {
/* don't print to screen if below log level */
if(screen_log_level > g_screen_log_level) return;
video_puts(message);
}
/**
* vprintk - logs a message and prints it to screen based on its screen_log_level
*
* If the level is below g_screen_log_level it will not be shown but logged to UART
* This text will not be colored or prefixed
* UART is TODO
*/
void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args)
{
char buf[PRINT_MESSAGE_MAX_LENGTH];
vsnprintf(buf, PRINT_MESSAGE_MAX_LENGTH, fmt, args);
/* we don't need that flag here, but if it gets used, strip it so we print correctly */
screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
/* log to UART */
log_to_uart(buf);
print_to_screen(screen_log_level, buf);
}
static void add_prefix(ScreenLogLevel screen_log_level, const char *fmt, char *buf) {
char typebuf[] = "[%s] %s";
/* apply prefix and append message format */
/* TODO: add coloring to the output */
switch(screen_log_level)
{
case SCREEN_LOG_LEVEL_ERROR:
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "ERROR", fmt);
break;
case SCREEN_LOG_LEVEL_WARNING:
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "WARNING", fmt);
break;
case SCREEN_LOG_LEVEL_MANDATORY:
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
break;
case SCREEN_LOG_LEVEL_INFO:
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "INFO", fmt);
break;
case SCREEN_LOG_LEVEL_DEBUG:
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, typebuf, "DEBUG", fmt);
break;
default:
break;
}
}
/**
* print - logs a message and prints it to screen based on its screen_log_level
*
* If the level is below g_screen_log_level it will not be shown but logged to UART
* Use SCREEN_LOG_LEVEL_NO_PREFIX if you don't want a prefix to be added
* UART is TODO
*/
void print(ScreenLogLevel screen_log_level, const char * fmt, ...)
{
char buf[PRINT_MESSAGE_MAX_LENGTH] = {};
char message[PRINT_MESSAGE_MAX_LENGTH] = {};
/* TODO: make splash disappear if level > MANDATORY */
/* make prefix free messages with log_level possible */
if(screen_log_level & SCREEN_LOG_LEVEL_NO_PREFIX) {
/* remove the NO_PREFIX flag so the enum can be recognized later on */
screen_log_level &= ~SCREEN_LOG_LEVEL_NO_PREFIX;
snprintf(buf, PRINT_MESSAGE_MAX_LENGTH, "%s", fmt);
}
else {
add_prefix(screen_log_level, fmt, buf);
}
/* input arguments */
va_list args;
va_start(args, fmt);
vsnprintf(message, PRINT_MESSAGE_MAX_LENGTH, buf, args);
va_end(args);
/* log to UART */
log_to_uart(message);
print_to_screen(screen_log_level, message);
}

43
fusee/fusee-mtc/src/lib/log.h
View file

@ -1,43 +0,0 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_LOG_H
#define FUSEE_LOG_H
#define PRINT_MESSAGE_MAX_LENGTH 1024
#include <stdarg.h>
typedef enum {
SCREEN_LOG_LEVEL_NONE = 0,
SCREEN_LOG_LEVEL_ERROR = 1,
SCREEN_LOG_LEVEL_WARNING = 2,
SCREEN_LOG_LEVEL_MANDATORY = 3, /* no log prefix */
SCREEN_LOG_LEVEL_INFO = 4,
SCREEN_LOG_LEVEL_DEBUG = 5,
SCREEN_LOG_LEVEL_NO_PREFIX = 0x100 /* OR this to your LOG_LEVEL to prevent prefix creation */
} ScreenLogLevel;
extern ScreenLogLevel g_screen_log_level;
void log_set_log_level(ScreenLogLevel screen_log_level);
ScreenLogLevel log_get_log_level();
void log_to_uart(const char *message);
void vprint(ScreenLogLevel screen_log_level, const char *fmt, va_list args);
void print(ScreenLogLevel screen_log_level, const char* fmt, ...);
#endif

2
fusee/fusee-mtc/src/main.c
View file

@ -17,7 +17,7 @@
#include <string.h>
#include "mtc.h"
#include "stage2.h"
#include "display/video_fb.h"
#include "../../../fusee/common/display/video_fb.h"
static void *g_framebuffer;
static __attribute__((__aligned__(0x200))) stage2_mtc_args_t g_mtc_args_store;

1
fusee/fusee-mtc/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32

51
fusee/fusee-mtc/src/mtc.c
View file

@ -21,7 +21,7 @@
#include "car.h"
#include "fuse.h"
#include "timers.h"
#include "lib/log.h"
#include "../../../fusee/common/log.h"
/*
* Macros.
@ -590,9 +590,12 @@ static const uint32_t g_ram_pattern_dmi[0x500] = {
0xA, 0x5, 0xC, 0x3, 0xA, 0x5, 0xC, 0x3
};
/*
* Register read/write helpers.
*/
/* Determine the current SoC for Mariko specific code. */
static bool is_soc_mariko() {
return (fuse_get_soc_type() == 1);
}
/* Register read/write helpers. */
static inline void emc_write(uint32_t val, uint32_t offset) {
MAKE_EMC_REG(offset) = val;
}
@ -664,10 +667,10 @@ static void ccfifo_write(uint32_t ccfifo_addr, uint32_t ccfifo_data, uint32_t cc
static void start_periodic_compensation() {
uint32_t mpc_req = 0x4B;
// Write to EMC_MPC_0
/* Write to EMC_MPC_0. */
emc_write(mpc_req, EMC_MPC);
// Dummy read
/* Dummy read. */
mpc_req = emc_read(EMC_MPC);
}
@ -704,7 +707,7 @@ static uint32_t wait_for_update(uint32_t status_reg, uint32_t bit_mask, bool upd
udelay(1);
}
// Timeout
/* Timeout. */
return 4;
}
@ -1114,9 +1117,7 @@ static uint32_t update_clock_tree_delay(tegra_emc_timing_t* current_timing, tegr
bool training_update = (type == TRAINING_UPDATE);
bool periodic_training_update = (type == PERIODIC_TRAINING_UPDATE);
/*
* Dev0 MSB.
*/
/* Dev0 MSB. */
if (dvfs_pt1 || training_pt1 || periodic_training_update) {
mrr_req = ((2 << EMC_MRR_DEV_SEL_SHIFT) | (19 << EMC_MRR_MA_SHIFT));
emc_write(mrr_req, EMC_MRR);
@ -1136,9 +1137,7 @@ static uint32_t update_clock_tree_delay(tegra_emc_timing_t* current_timing, tegr
temp1_1 = (mrr_data & 0xff00);
}
/*
* Dev0 LSB.
*/
/* Dev0 LSB. */
mrr_req = ((mrr_req & ~EMC_MRR_MA_MASK) | (18 << EMC_MRR_MA_SHIFT));
emc_write(mrr_req, EMC_MRR);
@ -1249,9 +1248,7 @@ static uint32_t update_clock_tree_delay(tegra_emc_timing_t* current_timing, tegr
if (dram_dev_num != TWO_RANK)
return adel;
/*
* Dev1 MSB.
*/
/* Dev1 MSB. */
if (dvfs_pt1 || training_pt1 || periodic_training_update) {
mrr_req = ((1 << EMC_MRR_DEV_SEL_SHIFT) | (19 << EMC_MRR_MA_SHIFT));
emc_write(mrr_req, EMC_MRR);
@ -1271,9 +1268,7 @@ static uint32_t update_clock_tree_delay(tegra_emc_timing_t* current_timing, tegr
temp1_1 = (mrr_data & 0xff00);
}
/*
* Dev1 LSB.
*/
/* Dev1 LSB. */
mrr_req = ((mrr_req & ~EMC_MRR_MA_MASK) | (18 << EMC_MRR_MA_SHIFT));
emc_write(mrr_req, EMC_MRR);
@ -1454,9 +1449,7 @@ static uint32_t periodic_compensation_handler(tegra_emc_timing_t *current_timing
start_periodic_compensation();
udelay(delay);
/*
* Generate next sample of data.
*/
/* Generate next sample of data. */
adel = update_clock_tree_delay(current_timing, next_timing, dram_dev_num, channel_mode, DVFS_PT1);
}
}
@ -1477,9 +1470,7 @@ static uint32_t periodic_compensation_handler(tegra_emc_timing_t *current_timing
start_periodic_compensation();
udelay(delay);
/*
* Generate next sample of data.
*/
/* Generate next sample of data. */
update_clock_tree_delay(current_timing, next_timing, dram_dev_num, channel_mode, TRAINING_PT1);
}
@ -3706,7 +3697,7 @@ static int train_one(int z_val, uint32_t next_rate, uint32_t current_rate, tegra
return 0;
}
void train_dram(void) {
static void train_dram_erista(void) {
volatile tegra_car_t *car = car_get_regs();
tegra_emc_timing_t *timing_tables;
@ -3747,4 +3738,12 @@ void train_dram(void) {
do_periodic_emc_compensation((tegra_emc_timing_t*)&timing_tables[g_active_timing_table_idx]);
print(SCREEN_LOG_LEVEL_DEBUG, "[MTC]: Done!\n");
}
void train_dram(void) {
if (is_soc_mariko()) {
/* TODO */
} else {
train_dram_erista();
}
}

1185
fusee/fusee-mtc/src/pmc.h
View file

File diff suppressed because it is too large Load diff

2
fusee/fusee-mtc/src/stage2.h
View file

@ -17,7 +17,7 @@
#ifndef FUSEE_STAGE2_H
#define FUSEE_STAGE2_H
#include "lib/log.h"
#include "../../../fusee/common/log.h"
#define MTC_ARGV_ARGUMENT_STRUCT 0
#define MTC_ARGC 1

4
fusee/fusee-mtc/src/utils.c
View file

@ -17,8 +17,8 @@
#include <stdbool.h>
#include <stdarg.h>
#include "utils.h"
#include "display/video_fb.h"
#include "lib/log.h"
#include "../../../fusee/common/display/video_fb.h"
#include "../../../fusee/common/log.h"
__attribute__ ((noreturn)) void generic_panic(void) {
while (true) {

45
fusee/fusee-primary/Makefile
View file

@ -8,7 +8,7 @@ endif
TOPDIR ?= $(CURDIR)
AMS := $(TOPDIR)/../../
AMS := $(TOPDIR)/../../../
include $(DEVKITARM)/base_rules
AMSBRANCH := $(shell git symbolic-ref --short HEAD)
@ -18,6 +18,13 @@ ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
AMSREV := $(AMSREV)-dirty
endif
define _bin2o
bin2s $< | $(AS) -o $(@)
echo "extern const u8" `(echo $(<F) | sed -e 's/^\([0-9]\)/_\1/' | tr . _ | tr - _)`"_end[];" > `(echo $(<F) | tr . _ | tr - _)`.h
echo "extern const u8" `(echo $(<F) | sed -e 's/^\([0-9]\)/_\1/' | tr . _ | tr - _)`"[];" >> `(echo $(<F) | tr . _ | tr - _)`.h
echo "extern const u32" `(echo $(<F) | sed -e 's/^\([0-9]\)/_\1/' | tr . _ | tr - _)`_size";" >> `(echo $(<F) | tr . _ | tr - _)`.h
endef
#---------------------------------------------------------------------------------
# TARGET is the name of the output
# BUILD is the directory where object files & intermediate files will be placed
@ -27,9 +34,9 @@ endif
#---------------------------------------------------------------------------------
TARGET := $(notdir $(CURDIR))
BUILD := build
SOURCES := src src/sdmmc src/lib src/lib/fatfs src/display
SOURCES := src
DATA := data
INCLUDES := include ../../libraries/libvapours/include
INCLUDES := include ../../../libraries/libvapours/include
#---------------------------------------------------------------------------------
# options for code generation
@ -77,14 +84,14 @@ export TOPDIR := $(CURDIR)
export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
$(AMS)/exosphere/program/rebootstub
$(CURDIR)/fusee-primary-main
export DEPSDIR := $(CURDIR)/$(BUILD)
CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) rebootstub.bin
BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) fusee-primary-main.lz4
#---------------------------------------------------------------------------------
# use CXX for linking C++ projects, CC for standard C
@ -100,10 +107,10 @@ else
endif
#---------------------------------------------------------------------------------
export OFILES_BIN := $(addsuffix .o,$(BINFILES))
export OFILES_BIN := $(addsuffix .o,$(subst -,_,$(BINFILES)))
export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
export OFILES := $(OFILES_BIN) $(OFILES_SRC)
export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES)))
export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(subst -,_,$(BINFILES))))
export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
@ -111,22 +118,24 @@ export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
.PHONY: $(BUILD) clean all check_rebootstub
.PHONY: $(BUILD) clean all check_main
#---------------------------------------------------------------------------------
all: check_rebootstub $(BUILD)
all: $(BUILD)
check_rebootstub:
@$(MAKE) -C $(AMS)/exosphere/program/rebootstub all
fusee-primary-main/fusee-primary-main.lz4: check_main
$(BUILD): check_rebootstub
check_main:
@$(MAKE) -C fusee-primary-main all
$(BUILD): fusee-primary-main/fusee-primary-main.lz4
@[ -d $@ ] || mkdir -p $@
@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
#---------------------------------------------------------------------------------
clean:
@echo clean ...
@$(MAKE) -C $(AMS)/exosphere/program/rebootstub clean
@$(MAKE) -C fusee-primary-main clean
@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
@ -152,6 +161,8 @@ $(OUTPUT).elf : $(OFILES)
@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
@$(NM) -CSn $@ > $(notdir $*.lst)
utils.o: CFLAGS += -fno-builtin
$(OFILES_SRC) : $(HFILES_BIN)
#---------------------------------------------------------------------------------
@ -162,6 +173,14 @@ $(OFILES_SRC) : $(HFILES_BIN)
@echo $(notdir $<)
@$(bin2o)
#---------------------------------------------------------------------------------
# you need a rule like this for each extension you use as binary data
#---------------------------------------------------------------------------------
fusee_primary_main.lz4.o fusee_primary_main_lz4.h: fusee-primary-main.lz4
#---------------------------------------------------------------------------------
@echo $(notdir $<)
@$(_bin2o)
-include $(DEPENDS)
#---------------------------------------------------------------------------------------

173
fusee/fusee-primary/fusee-primary-main/Makefile Normal file
View file

@ -0,0 +1,173 @@
#---------------------------------------------------------------------------------
.SUFFIXES:
#---------------------------------------------------------------------------------
ifeq ($(strip $(DEVKITARM)),)
$(error "Please set DEVKITARM in your environment. export DEVKITARM=<path to>devkitARM")
endif
TOPDIR ?= $(CURDIR)
AMS ?= $(TOPDIR)/../../../
include $(DEVKITARM)/base_rules
AMSBRANCH := $(shell git symbolic-ref --short HEAD)
AMSREV := $(AMSBRANCH)-$(shell git rev-parse --short HEAD)
ifneq (, $(strip $(shell git status --porcelain 2>/dev/null)))
AMSREV := $(AMSREV)-dirty
endif
#---------------------------------------------------------------------------------
# TARGET is the name of the output
# BUILD is the directory where object files & intermediate files will be placed
# SOURCES is a list of directories containing source code
# DATA is a list of directories containing data files
# INCLUDES is a list of directories containing header files
#---------------------------------------------------------------------------------
TARGET := $(notdir $(CURDIR))
BUILD := build
SOURCES := src ../../../fusee/common ../../../fusee/common/display ../../../fusee/common/fatfs ../../../fusee/common/sdmmc
DATA := data
INCLUDES := include ../../../libraries/libvapours/include
#---------------------------------------------------------------------------------
# options for code generation
#---------------------------------------------------------------------------------
ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork
DEFINES := -D__BPMP__ -DFUSEE_STAGE1_SRC -DATMOSPHERE_GIT_BRANCH=\"$(AMSBRANCH)\" -DATMOSPHERE_GIT_REV=\"$(AMSREV)\"
CFLAGS := \
-g \
-O2 \
-fomit-frame-pointer \
-ffunction-sections \
-fdata-sections \
-std=gnu11 \
-Werror \
-Wall \
-fstrict-volatile-bitfields \
$(ARCH) $(DEFINES)
CFLAGS += $(INCLUDE)
CXXFLAGS := $(CFLAGS) -fno-rtti -fno-exceptions -std=gnu++11
ASFLAGS := -g $(ARCH)
LDFLAGS = -specs=$(TOPDIR)/linker.specs -g $(ARCH) -Wl,-Map,$(notdir $*.map)
LIBS :=
#---------------------------------------------------------------------------------
# list of directories containing libraries, this must be the top level containing
# include and lib
#---------------------------------------------------------------------------------
LIBDIRS :=
#---------------------------------------------------------------------------------
# no real need to edit anything past this point unless you need to add additional
# rules for different file extensions
#---------------------------------------------------------------------------------
ifneq ($(BUILD),$(notdir $(CURDIR)))
#---------------------------------------------------------------------------------
export OUTPUT := $(CURDIR)/$(TARGET)
export TOPDIR := $(CURDIR)
export VPATH := $(foreach dir,$(SOURCES),$(CURDIR)/$(dir)) \
$(foreach dir,$(DATA),$(CURDIR)/$(dir)) \
$(AMS)/exosphere/program/rebootstub
export DEPSDIR := $(CURDIR)/$(BUILD)
CFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c)))
CPPFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.cpp)))
SFILES := $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.s)))
BINFILES := $(foreach dir,$(DATA),$(notdir $(wildcard $(dir)/*.*))) rebootstub.bin
#---------------------------------------------------------------------------------
# use CXX for linking C++ projects, CC for standard C
#---------------------------------------------------------------------------------
ifeq ($(strip $(CPPFILES)),)
#---------------------------------------------------------------------------------
export LD := $(CC)
#---------------------------------------------------------------------------------
else
#---------------------------------------------------------------------------------
export LD := $(CXX)
#---------------------------------------------------------------------------------
endif
#---------------------------------------------------------------------------------
export OFILES_BIN := $(addsuffix .o,$(BINFILES))
export OFILES_SRC := $(CPPFILES:.cpp=.o) $(CFILES:.c=.o) $(SFILES:.s=.o)
export OFILES := $(OFILES_BIN) $(OFILES_SRC)
export HFILES_BIN := $(addsuffix .h,$(subst .,_,$(BINFILES)))
export INCLUDE := $(foreach dir,$(INCLUDES),-I$(CURDIR)/$(dir)) \
$(foreach dir,$(LIBDIRS),-I$(dir)/include) \
-I$(CURDIR)/$(BUILD)
export LIBPATHS := $(foreach dir,$(LIBDIRS),-L$(dir)/lib)
.PHONY: $(BUILD) clean all check_rebootstub
#---------------------------------------------------------------------------------
all: check_rebootstub $(BUILD)
check_rebootstub:
@$(MAKE) -C $(AMS)/exosphere/program/rebootstub all
$(BUILD): check_rebootstub
@[ -d $@ ] || mkdir -p $@
@$(MAKE) --no-print-directory -C $(BUILD) -f $(CURDIR)/Makefile
#---------------------------------------------------------------------------------
clean:
@echo clean ...
@$(MAKE) -C $(AMS)/exosphere/program/rebootstub clean
@rm -fr $(BUILD) $(TARGET).bin $(TARGET).elf
#---------------------------------------------------------------------------------
else
.PHONY: all
DEPENDS := $(OFILES:.o=.d)
#---------------------------------------------------------------------------------
# main targets
#---------------------------------------------------------------------------------
all : $(OUTPUT).lz4
$(OUTPUT).lz4 : $(OUTPUT).bin
@python ../lz4_compress.py $(OUTPUT).bin $(OUTPUT).lz4
@echo built ... $(notdir $@)
$(OUTPUT).bin : $(OUTPUT).elf
$(OBJCOPY) -S -O binary $< $@
@echo built ... $(notdir $@)
$(OUTPUT).elf : $(OFILES)
%.elf: $(OFILES)
@echo linking $(notdir $@)
@$(LD) $(LDFLAGS) $(OFILES) $(LIBPATHS) $(LIBS) -o $@
@$(NM) -CSn $@ > $(notdir $*.lst)
$(OFILES_SRC) : $(HFILES_BIN)
#---------------------------------------------------------------------------------
# you need a rule like this for each extension you use as binary data
#---------------------------------------------------------------------------------
%.bin.o %_bin.h: %.bin
#---------------------------------------------------------------------------------
@echo $(notdir $<)
@$(bin2o)
-include $(DEPENDS)
#---------------------------------------------------------------------------------------
endif
#---------------------------------------------------------------------------------------

198
fusee/fusee-primary/fusee-primary-main/linker.ld Normal file
View file

@ -0,0 +1,198 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
PHDRS
{
crt0 PT_LOAD;
chainloader PT_LOAD;
main PT_LOAD;
}
/* Mostly copied from https://github.com/devkitPro/buildscripts/blob/master/dkarm-eabi/crtls/3dsx.ld */
MEMORY
{
NULL : ORIGIN = 0x00000000, LENGTH = 0x1000
main : ORIGIN = 0x40008000, LENGTH = 0x38000
low_iram : ORIGIN = 0x40000000, LENGTH = 0x6000
}
SECTIONS
{
PROVIDE(__start__ = 0x40008000);
PROVIDE(__stack_top__ = 0x40008000);
PROVIDE(__stack_bottom__ = 0x40006000);
PROVIDE(__heap_start__ = 0);
PROVIDE(__heap_end__ = 0);
. = __start__;
.crt0 :
{
KEEP( *(.text.start) )
KEEP( *(.init) )
. = ALIGN(32);
PROVIDE (__reboot_start__ = ABSOLUTE(.));
KEEP( *(.reboot*) )
. = ALIGN(4);
PROVIDE (__reboot_end__ = ABSOLUTE(.));
. = ALIGN(32);
} >main :crt0
.chainloader_loadable :
{
. = ALIGN(32);
PROVIDE (__chainloader_start__ = ABSOLUTE(.));
PROVIDE (__chainloader_lma__ = LOADADDR(.chainloader_loadable));
KEEP(*(.chainloader.text.start))
chainloader.o(.text*)
chainloader.o(.rodata*)
chainloader.o(.data*)
. = ALIGN(32);
} >low_iram AT>main :chainloader
.chainloader_bss (NOLOAD) :
{
. = ALIGN(32);
PROVIDE (__chainloader_bss_start__ = ABSOLUTE(.));
chainloader.o(.bss* COMMON)
. = ALIGN(32);
PROVIDE (__chainloader_end__ = ABSOLUTE(.));
} >low_iram :NONE
.text :
{
. = ALIGN(32);
/* .text */
*(.text.reboot_to_self)
*(.text)
*(.text.*)
*(.glue_7)
*(.glue_7t)
*(.stub)
*(.gnu.warning)
*(.gnu.linkonce.t*)
/* .fini */
KEEP( *(.fini) )
. = ALIGN(8);
} >main :main
.rodata :
{
*(.rodata)
*(.roda)
*(.rodata.*)
*all.rodata*(*)
*(.gnu.linkonce.r*)
SORT(CONSTRUCTORS)
. = ALIGN(8);
} >main
.preinit_array :
{
PROVIDE (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE (__preinit_array_end = .);
} >main
.init_array ALIGN(4) :
{
PROVIDE (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE (__init_array_end = .);
} >main
.fini_array ALIGN(4) :
{
PROVIDE (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE (__fini_array_end = .);
} >main
.ctors ALIGN(4) :
{
KEEP (*crtbegin.o(.ctors)) /* MUST be first -- GCC requires it */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
} >main
.dtors ALIGN(4) :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
} >main
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) __exidx_start = ABSOLUTE(.);} >main
ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = ABSOLUTE(.);} >main
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
CONSTRUCTORS
. = ALIGN(32);
} >main
.bss (NOLOAD) :
{
. = ALIGN(32);
PROVIDE (__bss_start__ = ABSOLUTE(.));
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(32);
PROVIDE (__bss_end__ = ABSOLUTE(.));
} >main :NONE
__end__ = ABSOLUTE(.) ;
/* ==================
==== Metadata ====
================== */
/* Discard sections that difficult post-processing */
/DISCARD/ : { *(.group .comment .note) }
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
}

7
fusee/fusee-primary/fusee-primary-main/linker.specs Normal file
View file

@ -0,0 +1,7 @@
%rename link old_link
*link:
%(old_link) -T %:getenv(TOPDIR /linker.ld) --nmagic --gc-sections
*startfile:
crti%O%s crtbegin%O%s

23
fusee/fusee-primary/fusee-primary-main/lz4_compress.py Normal file
View file

@ -0,0 +1,23 @@
#!/usr/bin/env python
import sys, lz4
from struct import unpack as up
def lz4_compress(data):
try:
import lz4.block as block
except ImportError:
block = lz4.LZ4_compress
return block.compress(data, 'high_compression', store_size=False)
def main(argc, argv):
if argc != 3:
print('Usage: %s in out' % argv[0])
return 1
with open(argv[1], 'rb') as f:
data = f.read()
with open(argv[2], 'wb') as f:
f.write(lz4_compress(data))
return 0
if __name__ == '__main__':
sys.exit(main(len(sys.argv), sys.argv))

31
fusee/fusee-primary/src/apb_misc.h → fusee/fusee-primary/fusee-primary-main/src/apb_misc.h
View file

@ -25,18 +25,33 @@
#define MAKE_APB_PADCTL_REG(n) MAKE_REG32(APB_PADCTL_BASE + n)
#define APB_MISC_PP_PINMUX_GLOBAL_0 MAKE_APB_MISC_REG(0x40)
#define APB_MISC_GP_DSI_PAD_CONTROL_0 MAKE_APB_MISC_REG(0xAC0)
#define APB_MISC_GP_WIFI_EN_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB64)
#define APB_MISC_GP_WIFI_RST_CFGPADCTRL_0 MAKE_APB_MISC_REG(0xB68)
#define SDMMC1_PAD_CAL_DRVUP_SHIFT (20)
#define SDMMC1_PAD_CAL_DRVDN_SHIFT (12)
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT (28)
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT (30)
#define SDMMC1_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVUP_SHIFT)
#define SDMMC1_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC1_PAD_CAL_DRVDN_SHIFT)
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWR_SHIFT)
#define SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_MASK (0x03u << SDMMC1_CLK_CFG_CAL_DRVDN_SLWF_SHIFT)
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT (8)
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT (2)
#define CFG2TMC_EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVUP_COMP_SHIFT)
#define CFG2TMC_EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << CFG2TMC_EMMC4_PAD_DRVDN_COMP_SHIFT)
#define EMMC2_PAD_DRVUP_COMP_SHIFT (8)
#define EMMC2_PAD_DRVDN_COMP_SHIFT (2)
#define EMMC2_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC2_PAD_DRVUP_COMP_SHIFT)
#define EMMC2_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC2_PAD_DRVDN_COMP_SHIFT)
#define SDMMC2_PAD_CAL_DRVUP_SHIFT (20)
#define SDMMC2_PAD_CAL_DRVDN_SHIFT (12)
#define SDMMC2_PAD_CAL_DRVUP_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVUP_SHIFT)
#define SDMMC2_PAD_CAL_DRVDN_MASK (0x7Fu << SDMMC2_PAD_CAL_DRVDN_SHIFT)
#define EMMC4_PAD_DRVUP_COMP_SHIFT (8)
#define EMMC4_PAD_DRVDN_COMP_SHIFT (2)
#define EMMC4_PAD_DRVUP_COMP_MASK (0x3Fu << EMMC4_PAD_DRVUP_COMP_SHIFT)
#define EMMC4_PAD_DRVDN_COMP_MASK (0x3Fu << EMMC4_PAD_DRVDN_COMP_SHIFT)
#define PADCTL_SDMMC1_DEEP_LOOPBACK (1 << 0)
#define PADCTL_SDMMC3_DEEP_LOOPBACK (1 << 0)
@ -53,22 +68,22 @@
typedef struct {
uint32_t asdbgreg; /* 0x810 */
uint32_t reserved0[0x31];
uint32_t _0x814[0x31];
uint32_t sdmmc1_clk_lpbk_control; /* 0x8D4 */
uint32_t sdmmc3_clk_lpbk_control; /* 0x8D8 */
uint32_t emmc2_pad_cfg_control; /* 0x8DC */
uint32_t emmc4_pad_cfg_control; /* 0x8E0 */
uint32_t _todo0[0x6E];
uint32_t _0x8E4[0x6E];
uint32_t sdmmc1_pad_cfgpadctrl; /* 0xA98 */
uint32_t emmc2_pad_cfgpadctrl; /* 0xA9C */
uint32_t emmc2_pad_drv_type_cfgpadctrl; /* 0xAA0 */
uint32_t emmc2_pad_pupd_cfgpadctrl; /* 0xAA4 */
uint32_t _todo1[0x03];
uint32_t _0xAA8[0x03];
uint32_t sdmmc3_pad_cfgpadctrl; /* 0xAB0 */
uint32_t emmc4_pad_cfgpadctrl; /* 0xAB4 */
uint32_t emmc4_pad_drv_type_cfgpadctrl; /* 0xAB8 */
uint32_t emmc4_pad_pupd_cfgpadctrl; /* 0xABC */
uint32_t _todo2[0x2E];
uint32_t _0xAC0[0x2E];
uint32_t vgpio_gpio_mux_sel; /* 0xB74 */
uint32_t qspi_sck_lpbk_control; /* 0xB78 */
} tegra_padctl_t;

0
fusee/fusee-primary/src/btn.c → fusee/fusee-primary/fusee-primary-main/src/btn.c
View file

0
fusee/fusee-primary/src/btn.h → fusee/fusee-primary/fusee-primary-main/src/btn.h
View file

3
fusee/fusee-primary/src/car.c → fusee/fusee-primary/fusee-primary-main/src/car.c
View file

@ -35,6 +35,7 @@ static inline uint32_t get_clk_source_reg(CarDevice dev) {
case CARDEVICE_KFUSE: return 0;
case CARDEVICE_CL_DVFS: return 0;
case CARDEVICE_CORESIGHT: return 0x1D4;
case CARDEVICE_MSELECT: return 0x3B4;
case CARDEVICE_ACTMON: return 0x3E8;
case CARDEVICE_BPMP: return 0;
default: generic_panic();
@ -58,6 +59,7 @@ static inline uint32_t get_clk_source_val(CarDevice dev) {
case CARDEVICE_KFUSE: return 0;
case CARDEVICE_CL_DVFS: return 0;
case CARDEVICE_CORESIGHT: return 0;
case CARDEVICE_MSELECT: return 0;
case CARDEVICE_ACTMON: return 6;
case CARDEVICE_BPMP: return 0;
default: generic_panic();
@ -81,6 +83,7 @@ static inline uint32_t get_clk_source_div(CarDevice dev) {
case CARDEVICE_KFUSE: return 0;
case CARDEVICE_CL_DVFS: return 0;
case CARDEVICE_CORESIGHT: return 4;
case CARDEVICE_MSELECT: return 6;
case CARDEVICE_ACTMON: return 0;
case CARDEVICE_BPMP: return 0;
default: generic_panic();

75
fusee/fusee-primary/src/car.h → fusee/fusee-primary/fusee-primary-main/src/car.h
View file

@ -37,23 +37,28 @@
/* Clock and reset devices. */
typedef enum {
CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_BPMP = ((0 << 5) | 0x1),
CARDEVICE_UARTA = ((0 << 5) | 0x6),
CARDEVICE_UARTB = ((0 << 5) | 0x7),
CARDEVICE_I2C1 = ((0 << 5) | 0xC),
CARDEVICE_USBD = ((0 << 5) | 0x16),
CARDEVICE_HOST1X = ((0 << 5) | 0x1C),
CARDEVICE_AHBDMA = ((1 << 5) | 0x1),
CARDEVICE_APBDMA = ((1 << 5) | 0x2),
CARDEVICE_KFUSE = ((1 << 5) | 0x8),
CARDEVICE_I2C5 = ((1 << 5) | 0xF),
CARDEVICE_UARTC = ((1 << 5) | 0x17),
CARDEVICE_USB2 = ((1 << 5) | 0x1A),
CARDEVICE_CORESIGHT = ((2 << 5) | 0x9),
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_BPMP = ((0 << 5) | 0x1)
CARDEVICE_TSEC = ((2 << 5) | 0x13),
CARDEVICE_MSELECT = ((3 << 5) | 0x8),
CARDEVICE_ACTMON = ((3 << 5) | 0x17),
CARDEVICE_TZRAM = ((3 << 5) | 0x1E),
CARDEVICE_SE = ((3 << 5) | 0x1F),
CARDEVICE_CL_DVFS = ((4 << 5) | 0x1B),
CARDEVICE_SOR0 = ((5 << 5) | 0x16),
CARDEVICE_SOR1 = ((5 << 5) | 0x17),
CARDEVICE_SOR_SAFE = ((6 << 5) | 0x1E),
} CarDevice;
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -97,31 +102,31 @@ typedef struct {
uint32_t pllc_out;
uint32_t pllc_misc0;
uint32_t pllc_misc1;
/* PLLM 0x90-0x9c */
uint32_t pllm_base;
uint32_t pllm_out;
uint32_t pllm_misc1;
uint32_t pllm_misc2;
/* PLLP 0xa0-0xac */
uint32_t pllp_base;
uint32_t pllp_outa;
uint32_t pllp_outb;
uint32_t pllp_misc;
/* PLLA 0xb0-0xbc */
uint32_t plla_base;
uint32_t plla_out;
uint32_t plla_misc0;
uint32_t plla_misc1;
/* PLLU 0xc0-0xcc */
uint32_t pllu_base;
uint32_t pllu_out;
uint32_t pllu_misc1;
uint32_t pllu_misc2;
/* PLLD 0xd0-0xdc */
uint32_t plld_base;
uint32_t plld_out;
@ -131,13 +136,13 @@ typedef struct {
/* PLLX 0xe0-0xe4 */
uint32_t pllx_base;
uint32_t pllx_misc;
/* PLLE 0xe8-0xf4 */
uint32_t plle_base;
uint32_t plle_misc;
uint32_t plle_ss_cntl1;
uint32_t plle_ss_cntl2;
uint32_t lvl2_clk_gate_ovra; /* _LVL2_CLK_GATE_OVRA_0, 0xf8 */
uint32_t lvl2_clk_gate_ovrb; /* _LVL2_CLK_GATE_OVRB_0, 0xfc */
@ -188,7 +193,7 @@ typedef struct {
uint32_t _0x1e0[5];
uint32_t clk_source_tsec; /* _CLK_SOURCE_TSEC_0, 0x1f4 */
uint32_t _0x1f8;
uint32_t clk_spare2; /* _CLK_SPARE2_0, 0x1fc */
uint32_t _0x200[32];
@ -257,7 +262,7 @@ typedef struct {
uint32_t lvl2_clk_gate_ovrc; /* _LVL2_CLK_GATE_OVRC, 0x3a0 */
uint32_t lvl2_clk_gate_ovrd; /* _LVL2_CLK_GATE_OVRD, 0x3a4 */
uint32_t _0x3a8[2];
uint32_t _0x3b0;
uint32_t clk_source_mselect; /* _CLK_SOURCE_MSELECT_0, 0x3b4 */
uint32_t clk_source_tsensor; /* _CLK_SOURCE_TSENSOR_0, 0x3b8 */
@ -283,7 +288,7 @@ typedef struct {
uint32_t clk_source_sata_oob; /* _CLK_SOURCE_SATA_OOB_0, 0x420 */
uint32_t clk_source_sata; /* _CLK_SOURCE_SATA_0, 0x424 */
uint32_t clk_source_hda; /* _CLK_SOURCE_HDA_0, 0x428 */
uint32_t _0x42c;
uint32_t clk_source_se; /* _CLK_SOURCE_SE_0, 0x42c */
/* _RST_DEV_V/W_SET_0 0x430-0x43c */
uint32_t rst_dev_v_set;
@ -371,13 +376,13 @@ typedef struct {
uint32_t spare_reg0; /* _SPARE_REG0_0, 0x55c */
uint32_t audio_sync_clk_dmic1; /* _AUDIO_SYNC_CLK_DMIC1_0, 0x560 */
uint32_t audio_sync_clk_dmic2; /* _AUDIO_SYNC_CLK_DMIC2_0, 0x564 */
uint32_t _0x568[2];
uint32_t plld2_ss_cfg; /* _PLLD2_SS_CFG, 0x570 */
uint32_t plld2_ss_ctrl1; /* _PLLD2_SS_CTRL1_0, 0x574 */
uint32_t plld2_ss_ctrl2; /* _PLLD2_SS_CTRL2_0, 0x578 */
uint32_t _0x57c[5];
uint32_t plldp_base; /* _PLLDP_BASE, 0x590*/
uint32_t plldp_misc; /* _PLLDP_MISC, 0x594 */
uint32_t plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
@ -399,7 +404,7 @@ typedef struct {
uint32_t pllx_misc4; /* _PLLX_MISC_4_0, 0x5f0 */
uint32_t pllx_misc5; /* _PLLX_MISC_5_0, 0x5f4 */
uint32_t _0x5f8[2];
uint32_t clk_source_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST_0, 0x600 */
uint32_t clk_source_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON_0, 0x604 */
uint32_t clk_source_xusb_fs; /* _CLK_SOURCE_XUSB_FS_0, 0x608 */
@ -428,7 +433,7 @@ typedef struct {
uint32_t clk_source_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIPI_CAL_0, 0x66c */
uint32_t _0x670[2];
uint32_t clk_source_vic; /* _CLK_SOURCE_VIC_0, 0x678 */
uint32_t pllp_outc; /* _PLLP_OUTC_0, 0x67c */
uint32_t pllp_misc1; /* _PLLP_MISC1_0, 0x680 */
uint32_t _0x684[2];
@ -439,14 +444,14 @@ typedef struct {
uint32_t clk_source_nvdec; /* _CLK_SOURCE_NVDEC_0, 0x698 */
uint32_t clk_source_nvjpg; /* _CLK_SOURCE_NVJPG_0, 0x69c */
uint32_t clk_source_nvenc; /* _CLK_SOURCE_NVENC_0, 0x6a0 */
uint32_t plla1_base; /* _PLLA1_BASE_0, 0x6a4 */
uint32_t plla1_misc0; /* _PLLA1_MISC_0_0, 0x6a8 */
uint32_t plla1_misc1; /* _PLLA1_MISC_1_0, 0x6ac */
uint32_t plla1_misc2; /* _PLLA1_MISC_2_0, 0x6b0 */
uint32_t plla1_misc3; /* _PLLA1_MISC_3_0, 0x6b4 */
uint32_t audio_sync_clk_dmic3; /* _AUDIO_SYNC_CLK_DMIC3_0, 0x6b8 */
uint32_t clk_source_dmic3; /* _CLK_SOURCE_DMIC3_0, 0x6bc */
uint32_t clk_source_ape; /* _CLK_SOURCE_APE_0, 0x6c0 */
uint32_t clk_source_qspi; /* _CLK_SOURCE_QSPI_0, 0x6c4 */
@ -455,11 +460,11 @@ typedef struct {
uint32_t clk_source_pex_sata_usb_rx_byp; /* _CLK_SOURCE_PEX_SATA_USB_RX_BYP_0, 0x6d0 */
uint32_t clk_source_maud; /* _CLK_SOURCE_MAUD_0, 0x6d4 */
uint32_t clk_source_tsecb; /* _CLK_SOURCE_TSECB_0, 0x6d8 */
uint32_t clk_cpug_misc1; /* _CLK_CPUG_MISC1_0, 0x6dc */
uint32_t aclk_burst_policy; /* _ACLK_BURST_POLICY_0, 0x6e0 */
uint32_t super_aclk_divider; /* _SUPER_ACLK_DIVIDER_0, 0x6e4 */
uint32_t nvenc_super_clk_divider; /* _NVENC_SUPER_CLK_DIVIDER_0, 0x6e8 */
uint32_t vi_super_clk_divider; /* _VI_SUPER_CLK_DIVIDER_0, 0x6ec */
uint32_t vic_super_clk_divider; /* _VIC_SUPER_CLK_DIVIDER_0, 0x6f0 */
@ -470,7 +475,7 @@ typedef struct {
uint32_t se_super_clk_divider; /* _SE_SUPER_CLK_DIVIDER_0, 0x704 */
uint32_t tsec_super_clk_divider; /* _TSEC_SUPER_CLK_DIVIDER_0, 0x708 */
uint32_t tsecb_super_clk_divider; /* _TSECB_SUPER_CLK_DIVIDER_0, 0x70c */
uint32_t clk_source_uartape; /* _CLK_SOURCE_UARTAPE_0, 0x710 */
uint32_t clk_cpug_misc2; /* _CLK_CPUG_MISC2_0, 0x714 */
uint32_t clk_source_dbgapb; /* _CLK_SOURCE_DBGAPB_0, 0x718 */

0
fusee/fusee-primary/src/chainloader.c → fusee/fusee-primary/fusee-primary-main/src/chainloader.c
View file

4
fusee/fusee-primary/src/chainloader.h → fusee/fusee-primary/fusee-primary-main/src/chainloader.h
View file

@ -13,14 +13,14 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_CHAINLOADER_H
#define FUSEE_CHAINLOADER_H
#include <stddef.h>
#include <stdint.h>
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x6200
#define CHAINLOADER_ARG_DATA_MAX_SIZE 0x5400
#define CHAINLOADER_MAX_ENTRIES 128
typedef struct chainloader_entry_t {

465
fusee/fusee-primary/fusee-primary-main/src/di.c Normal file
View file

@ -0,0 +1,465 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018 CTCaer
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include "di.h"
#include "fuse.h"
#include "timers.h"
#include "i2c.h"
#include "pmc.h"
#include "max77620.h"
#include "gpio.h"
#include "pinmux.h"
#include "car.h"
#include "apb_misc.h"
#include "di.inl"
static uint32_t g_lcd_vendor = 0;
/* Determine the current SoC for Mariko specific code. */
static bool is_soc_mariko() {
return (fuse_get_soc_type() == 1);
}
static void do_dsi_sleep_or_register_writes(const dsi_sleep_or_register_write_t *writes, uint32_t num_writes) {
for (uint32_t i = 0; i < num_writes; i++) {
if (writes[i].kind == 1) {
udelay(1000 * writes[i].offset);
} else {
*(volatile uint32_t *)(DSI_BASE + sizeof(uint32_t) * writes[i].offset) = writes[i].value;
}
}
}
static void do_register_writes(uint32_t base_address, const register_write_t *writes, uint32_t num_writes) {
for (uint32_t i = 0; i < num_writes; i++) {
*(volatile uint32_t *)(base_address + writes[i].offset) = writes[i].value;
}
}
static void dsi_wait(uint32_t timeout, uint32_t offset, uint32_t mask, uint32_t delay) {
uint32_t end = get_time_us() + timeout;
while ((get_time_us() < end) && (MAKE_DSI_REG(offset) & mask)) {
/* Wait. */
}
udelay(delay);
}
void display_init(void) {
volatile tegra_car_t *car = car_get_regs();
volatile tegra_pmc_t *pmc = pmc_get_regs();
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
bool is_mariko = is_soc_mariko();
uint32_t hardware_type = fuse_get_hardware_type();
/* Power on. */
if (is_mariko) {
uint8_t val = 0x3A;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2, &val, 1);
val = 0x71;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD2_CFG, &val, 1);
val = 0xD0;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1);
} else {
uint8_t val = 0xD0;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO0_CFG, &val, 1);
}
/* Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks. */
car->rst_dev_h_clr = 0x1010000;
car->clk_enb_h_set = 0x1010000;
car->rst_dev_l_clr = 0x18000000;
car->clk_enb_l_set = 0x18000000;
car->clk_enb_x_set = 0x20000;
car->clk_source_uart_fst_mipi_cal = 0xA;
car->clk_enb_w_set = 0x80000;
car->clk_source_dsia_lp = 0xA;
/* DPD idle. */
pmc->io_dpd_req = 0x40000000;
pmc->io_dpd2_req = 0x40000000;
/* Configure pins. */
pinmux->nfc_en &= ~PINMUX_TRISTATE;
pinmux->nfc_int &= ~PINMUX_TRISTATE;
pinmux->lcd_bl_pwm &= ~PINMUX_TRISTATE;
pinmux->lcd_bl_en &= ~PINMUX_TRISTATE;
pinmux->lcd_rst &= ~PINMUX_TRISTATE;
if (is_mariko && (hardware_type == 5)) {
/* HardwareType_Five only configures GPIO_LCD_BL_RST. */
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
} else {
/* Configure Backlight +-5V GPIOs. */
gpio_configure_mode(GPIO_LCD_BL_P5V, GPIO_MODE_GPIO);
gpio_configure_mode(GPIO_LCD_BL_N5V, GPIO_MODE_GPIO);
gpio_configure_direction(GPIO_LCD_BL_P5V, GPIO_DIRECTION_OUTPUT);
gpio_configure_direction(GPIO_LCD_BL_N5V, GPIO_DIRECTION_OUTPUT);
/* Enable Backlight +5V. */
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_HIGH);
udelay(10000);
/* Enable Backlight -5V. */
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_HIGH);
udelay(10000);
/* Configure Backlight PWM, EN and RST GPIOs. */
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_GPIO);
gpio_configure_mode(GPIO_LCD_BL_EN, GPIO_MODE_GPIO);
gpio_configure_mode(GPIO_LCD_BL_RST, GPIO_MODE_GPIO);
gpio_configure_direction(GPIO_LCD_BL_PWM, GPIO_DIRECTION_OUTPUT);
gpio_configure_direction(GPIO_LCD_BL_EN, GPIO_DIRECTION_OUTPUT);
gpio_configure_direction(GPIO_LCD_BL_RST, GPIO_DIRECTION_OUTPUT);
/* Enable Backlight EN. */
gpio_write(GPIO_LCD_BL_EN, GPIO_LEVEL_HIGH);
}
/* Configure display interface and display. */
MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
if (is_mariko) {
MAKE_MIPI_CAL_REG(MIPI_CAL_MIPI_BIAS_PAD_CFG0) = 0;
APB_MISC_GP_DSI_PAD_CONTROL_0 = 0;
}
if (is_mariko) {
do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
} else {
do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
}
do_register_writes(DI_BASE, display_config_dc_01, 94);
do_register_writes(DSI_BASE, display_config_dsi_01_init_01, 8);
if (is_mariko) {
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_mariko, 1);
} else {
do_register_writes(DSI_BASE, display_config_dsi_01_init_02_erista, 1);
}
do_register_writes(DSI_BASE, display_config_dsi_01_init_03, 14);
if (is_mariko) {
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_mariko, 7);
} else {
do_register_writes(DSI_BASE, display_config_dsi_01_init_04_erista, 0);
}
do_register_writes(DSI_BASE, display_config_dsi_01_init_05, 10);
if (is_mariko) {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
} else {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
}
do_register_writes(DSI_BASE, display_config_dsi_01_init_06, 12);
if (is_mariko) {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
} else {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
}
do_register_writes(DSI_BASE, display_config_dsi_01_init_07, 14);
udelay(10000);
/* Enable Backlight RST. */
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_HIGH);
udelay(60000);
if (is_mariko && (hardware_type == 5)) {
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x40103;
} else {
MAKE_DSI_REG(DSI_BTA_TIMING) = 0x50204;
}
MAKE_DSI_REG(DSI_WR_DATA) = 0x337;
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
MAKE_DSI_REG(DSI_WR_DATA) = 0x406;
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
dsi_wait(250000, DSI_TRIGGER, (DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO), 5);
MAKE_DSI_REG(DSI_HOST_CONTROL) = (DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC);
dsi_wait(150000, DSI_HOST_CONTROL, DSI_HOST_CONTROL_IMM_BTA, 5000);
/* Parse LCD vendor. */
uint32_t host_response[3];
for (uint32_t i = 0; i < 3; i++) {
host_response[i] = MAKE_DSI_REG(DSI_RD_DATA);
}
/* The last word from host response is:
Bits 0-7: FAB
Bits 8-15: REV
Bits 16-23: Minor REV
*/
if ((host_response[2] & 0xFF) == 0x10) {
g_lcd_vendor = 0;
} else {
g_lcd_vendor = (host_response[2] >> 8) & 0xFF00;
}
g_lcd_vendor = (g_lcd_vendor & 0xFFFFFF00) | (host_response[2] & 0xFF);
/* LCD vendor specific configuration. */
switch (g_lcd_vendor) {
case 0x10: /* Japan Display Inc screens. */
do_dsi_sleep_or_register_writes(display_config_jdi_specific_init_01, 48);
break;
case 0xF20: /* Innolux nx-abca2 screens. */
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abca2_specific_init_01, 14);
break;
case 0xF30: /* AUO nx-abca2 screens. */
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_init_01, 14);
break;
case 0x2050: /* Unknown nx-abcd screens. */
do_dsi_sleep_or_register_writes(display_config_50_nx_abcd_specific_init_01, 13);
break;
case 0x1020: /* Innolux nx-abcc screens. */
case 0x1030: /* AUO nx-abcc screens. */
case 0x1040: /* Unknown nx-abcc screens. */
default:
do_dsi_sleep_or_register_writes(display_config_innolux_auo_40_nx_abcc_specific_init_01, 5);
break;
}
udelay(20000);
if (is_mariko) {
do_register_writes(CAR_BASE, display_config_plld_02_mariko, 3);
} else {
do_register_writes(CAR_BASE, display_config_plld_02_erista, 3);
}
do_register_writes(DSI_BASE, display_config_dsi_01_init_08, 1);
if (is_mariko) {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
} else {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
}
do_register_writes(DSI_BASE, display_config_dsi_01_init_09, 19);
MAKE_DI_REG(DC_DISP_DISP_CLOCK_CONTROL) = 4;
do_register_writes(DSI_BASE, display_config_dsi_01_init_10, 10);
udelay(10000);
if (is_mariko) {
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2);
do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_mariko, 2);
do_register_writes(DSI_BASE, display_config_dsi_01_init_11_mariko, 7);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_mariko, 6);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10);
} else {
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_01, 4);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_02_erista, 2);
do_register_writes(DSI_BASE, display_config_dsi_01_init_11_erista, 4);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_03_erista, 6);
do_register_writes(MIPI_CAL_BASE, display_config_mipi_cal_04, 10);
}
udelay(10000);
do_register_writes(DI_BASE, display_config_dc_02, 113);
}
void display_end(void) {
volatile tegra_car_t *car = car_get_regs();
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
bool is_mariko = is_soc_mariko();
/* Disable Backlight. */
display_backlight(false);
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
MAKE_DSI_REG(DSI_WR_DATA) = 0x2805;
/* Wait 5 frames. */
uint32_t start_val = MAKE_HOST1X_REG(0x30A4);
while (MAKE_HOST1X_REG(0x30A4) < start_val + 5) {
/* Wait. */
}
MAKE_DI_REG(DC_CMD_STATE_ACCESS) = (READ_MUX | WRITE_MUX);
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
do_register_writes(DI_BASE, display_config_dc_01_fini_01, 13);
udelay(40000);
if (is_mariko) {
do_register_writes(CAR_BASE, display_config_plld_01_mariko, 4);
} else {
do_register_writes(CAR_BASE, display_config_plld_01_erista, 4);
}
do_register_writes(DSI_BASE, display_config_dsi_01_fini_01, 2);
if (is_mariko) {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_mariko, 1);
} else {
do_register_writes(DSI_BASE, display_config_dsi_phy_timing_erista, 1);
}
do_register_writes(DSI_BASE, display_config_dsi_01_fini_02, 13);
if (g_lcd_vendor != 0x2050) {
udelay(10000);
}
/* LCD vendor specific shutdown. */
switch (g_lcd_vendor) {
case 0x10: /* Japan Display Inc screens. */
do_dsi_sleep_or_register_writes(display_config_jdi_specific_fini_01, 22);
break;
case 0xF30: /* AUO nx-abca2 screens. */
do_dsi_sleep_or_register_writes(display_config_auo_nx_abca2_specific_fini_01, 38);
break;
case 0x1020: /* Innolux nx-abcc screens. */
do_dsi_sleep_or_register_writes(display_config_innolux_nx_abcc_specific_fini_01, 10);
break;
case 0x1030: /* AUO nx-abcc screens. */
do_dsi_sleep_or_register_writes(display_config_auo_nx_abcc_specific_fini_01, 10);
break;
case 0x1040: /* Unknown nx-abcc screens. */
do_dsi_sleep_or_register_writes(display_config_40_nx_abcc_specific_fini_01, 10);
break;
default:
break;
}
MAKE_DSI_REG(DSI_WR_DATA) = 0x1005;
MAKE_DSI_REG(DSI_TRIGGER) = DSI_TRIGGER_HOST;
udelay((g_lcd_vendor == 0x2050) ? 120000 : 50000);
/* Disable Backlight RST. */
gpio_write(GPIO_LCD_BL_RST, GPIO_LEVEL_LOW);
if (g_lcd_vendor == 0x2050) {
udelay(30000);
} else {
udelay(10000);
/* Disable Backlight -5V. */
gpio_write(GPIO_LCD_BL_N5V, GPIO_LEVEL_LOW);
udelay(10000);
/* Disable Backlight +5V. */
gpio_write(GPIO_LCD_BL_P5V, GPIO_LEVEL_LOW);
udelay(10000);
}
/* Disable clocks. */
car->rst_dev_h_set = 0x1010000;
car->clk_enb_h_clr = 0x1010000;
car->rst_dev_l_set = 0x18000000;
car->clk_enb_l_clr = 0x18000000;
MAKE_DSI_REG(DSI_PAD_CONTROL_0) = (DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF));
MAKE_DSI_REG(DSI_POWER_CONTROL) = 0;
if (!is_mariko) {
/* Backlight PWM. */
gpio_configure_mode(GPIO_LCD_BL_PWM, GPIO_MODE_SFIO);
pinmux->lcd_bl_pwm = ((pinmux->lcd_bl_pwm & ~PINMUX_TRISTATE) | PINMUX_TRISTATE);
pinmux->lcd_bl_pwm = (((pinmux->lcd_bl_pwm >> 2) << 2) | 1);
}
}
void display_backlight(bool enable) {
if (g_lcd_vendor == 0x2050) {
int brightness = enable ? 100 : 0;
/* Enable FRAME_END_INT */
MAKE_DI_REG(DC_CMD_INT_ENABLE) = 2;
/* Configure DSI_LINE_TYPE as FOUR */
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 1;
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 9;
/* Set and wait for FRAME_END_INT */
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
/* Wait */
}
/* Configure display brightness. */
const uint32_t brightness_val = ((0x7FF * brightness) / 100);
MAKE_DSI_REG(DSI_WR_DATA) = 0x339;
MAKE_DSI_REG(DSI_WR_DATA) = (brightness_val & 0x700) | ((brightness_val & 0xFF) << 16) | 0x51;
/* Set and wait for FRAME_END_INT */
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
while ((MAKE_DI_REG(DC_CMD_INT_STATUS) & 2) != 0) {
/* Wait */
}
/* Set client sync point block reset. */
MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 1;
udelay(300000);
/* Clear client sync point block resest. */
MAKE_DSI_REG(DSI_INCR_SYNCPT_CNTRL) = 0;
udelay(300000);
/* Clear DSI_LINE_TYPE config. */
MAKE_DSI_REG(DSI_VIDEO_MODE_CONTROL) = 0;
/* Disable FRAME_END_INT */
MAKE_DI_REG(DC_CMD_INT_ENABLE) = 0;
MAKE_DI_REG(DC_CMD_INT_STATUS) = 2;
} else {
/* Enable Backlight PWM. */
gpio_write(GPIO_LCD_BL_PWM, enable ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW);
}
}
void display_color_screen(uint32_t color) {
do_register_writes(DI_BASE, display_config_solid_color, 8);
/* Configure display to show single color. */
MAKE_DI_REG(DC_WIN_AD_WIN_OPTIONS) = 0;
MAKE_DI_REG(DC_WIN_BD_WIN_OPTIONS) = 0;
MAKE_DI_REG(DC_WIN_CD_WIN_OPTIONS) = 0;
MAKE_DI_REG(DC_DISP_BLEND_BACKGROUND_COLOR) = color;
MAKE_DI_REG(DC_CMD_STATE_CONTROL) = ((MAKE_DI_REG(DC_CMD_STATE_CONTROL) & 0xFFFFFFFE) | GENERAL_ACT_REQ);
udelay(35000);
display_backlight(true);
}
uint32_t *display_init_framebuffer(void *address) {
static register_write_t conf[sizeof(display_config_frame_buffer)/sizeof(register_write_t)] = {0};
if (conf[0].value == 0) {
for (uint32_t i = 0; i < sizeof(display_config_frame_buffer)/sizeof(register_write_t); i++) {
conf[i] = display_config_frame_buffer[i];
}
}
uint32_t *lfb_addr = (uint32_t *)address;
conf[19].value = (uint32_t)address;
/* This configures the framebuffer @ address with a resolution of 1280x720 (line stride 768). */
do_register_writes(DI_BASE, conf, 32);
udelay(35000);
return lfb_addr;
}

56
fusee/fusee-primary/src/di.h → fusee/fusee-primary/fusee-primary-main/src/di.h
View file

@ -15,7 +15,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_DI_H_
#define FUSEE_DI_H_
@ -33,6 +33,12 @@
#define MAKE_MIPI_CAL_REG(n) MAKE_REG32(MIPI_CAL_BASE + n)
#define MAKE_VIC_REG(n) MAKE_REG32(VIC_BASE + n)
/* Clock and reset registers. */
#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138
#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
/* Display registers. */
#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
@ -60,6 +66,7 @@
#define PM0_ENABLE (1 << 16)
#define PM1_ENABLE (1 << 18)
#define DC_CMD_INT_STATUS 0x37
#define DC_CMD_INT_MASK 0x38
#define DC_CMD_INT_ENABLE 0x39
@ -238,6 +245,7 @@
#define DC_WIN_LINE_STRIDE 0x70A
#define DC_WIN_DV_CONTROL 0x70E
#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
/* The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
#define DC_WINBUF_START_ADDR 0x800
@ -246,6 +254,8 @@
#define DC_WINBUF_SURFACE_KIND 0x80B
/* Display serial interface registers. */
#define DSI_INCR_SYNCPT_CNTRL 0x1
#define DSI_RD_DATA 0x9
#define DSI_WR_DATA 0xA
@ -333,7 +343,7 @@
#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
#define DSI_PAD_CONTROL_CD 0x4c
#define DSI_PAD_CONTROL_CD 0x4C
#define DSI_VIDEO_MODE_CONTROL 0x4E
#define DSI_PAD_CONTROL_1 0x4F
@ -346,22 +356,44 @@
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
#define DSI_PAD_CONTROL_4 0x52
#define DSI_PAD_CONTROL_5_MARIKO 0x53
#define DSI_PAD_CONTROL_6_MARIKO 0x54
#define DSI_PAD_CONTROL_7_MARIKO 0x55
#define DSI_INIT_SEQ_DATA_15 0x5F
#define DSI_INIT_SEQ_DATA_15_MARIKO 0x62
typedef struct _cfg_op_t
{
uint32_t off;
uint32_t val;
} cfg_op_t;
/* MIPI calibration registers. */
#define MIPI_CAL_MIPI_CAL_CTRL 0x0
#define MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0 0x4
#define MIPI_CAL_CIL_MIPI_CAL_STATUS 0x8
#define MIPI_CAL_CIL_MIPI_CAL_STATUS_2 0xC
#define MIPI_CAL_CILA_MIPI_CAL_CONFIG 0x14
#define MIPI_CAL_CILB_MIPI_CAL_CONFIG 0x18
#define MIPI_CAL_CILC_MIPI_CAL_CONFIG 0x1C
#define MIPI_CAL_CILD_MIPI_CAL_CONFIG 0x20
#define MIPI_CAL_CILE_MIPI_CAL_CONFIG 0x24
#define MIPI_CAL_CILF_MIPI_CAL_CONFIG 0x28
#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG 0x38
#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG 0x3C
#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG 0x40
#define MIPI_CAL_DSID_MIPI_CAL_CONFIG 0x44
#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 0x58
#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 0x5C
#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60
#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 0x64
#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 0x68
#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 0x70
#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 0x74
void display_init();
void display_end();
/* Show one single color on the display. */
void display_color_screen(uint32_t color);
void display_init(void);
void display_end(void);
/* Switches screen backlight ON/OFF. */
void display_backlight(bool enable);
/* Show one single color on the display. */
void display_color_screen(uint32_t color);
/* Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
uint32_t *display_init_framebuffer(void *address);

773
fusee/fusee-primary/fusee-primary-main/src/di.inl Normal file
View file

@ -0,0 +1,773 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018 CTCaer
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
typedef struct {
uint32_t offset;
uint32_t value;
} register_write_t;
typedef struct {
uint16_t kind;
uint16_t offset;
uint32_t value;
} dsi_sleep_or_register_write_t;
static const uint32_t display_config_frame_buffer_address = 0xC0000000;
static const register_write_t display_config_plld_01_erista[4] = {
{CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000},
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA},
};
static const register_write_t display_config_plld_01_mariko[4] = {
{CLK_RST_CONTROLLER_CLK_SOURCE_DISP1, 0x40000000},
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4830A001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00},
};
static const register_write_t display_config_dc_01[94] = {
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_REG_ACT_CONTROL, 0x54},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_DISP_DC_MCCIF_FIFOCTRL, 0},
{sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY, 0},
{sizeof(uint32_t) * DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE},
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL},
{sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(uint32_t) * DC_WIN_CSC_KUR, 0},
{sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198},
{sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204},
{sizeof(uint32_t) * DC_WIN_CSC_KVB, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(uint32_t) * DC_WIN_CSC_KUR, 0},
{sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198},
{sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204},
{sizeof(uint32_t) * DC_WIN_CSC_KVB, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(uint32_t) * DC_WIN_CSC_KUR, 0},
{sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198},
{sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204},
{sizeof(uint32_t) * DC_WIN_CSC_KVB, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
{sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0},
{sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
};
static const register_write_t display_config_dsi_01_init_01[8] = {
{sizeof(uint32_t) * DSI_WR_DATA, 0x0},
{sizeof(uint32_t) * DSI_INT_ENABLE, 0x0},
{sizeof(uint32_t) * DSI_INT_STATUS, 0x0},
{sizeof(uint32_t) * DSI_INT_MASK, 0x0},
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_0, 0x0},
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_1, 0x0},
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_2, 0x0},
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_3, 0x0},
};
static const register_write_t display_config_dsi_01_init_02_erista[1] = {
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15, 0x0},
};
static const register_write_t display_config_dsi_01_init_02_mariko[1] = {
{sizeof(uint32_t) * DSI_INIT_SEQ_DATA_15_MARIKO, 0x0},
};
static const register_write_t display_config_dsi_01_init_03[14] = {
{sizeof(uint32_t) * DSI_DCS_CMDS, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_0_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_1_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_2_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_4_HI, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0},
{sizeof(uint32_t) * DSI_CONTROL, 0},
};
static const register_write_t display_config_dsi_01_init_04_erista[0] = {
/* No register writes. */
};
static const register_write_t display_config_dsi_01_init_04_mariko[7] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
};
static const register_write_t display_config_dsi_01_init_05[10] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_CD, 0},
{sizeof(uint32_t) * DSI_SOL_DELAY, 0x18},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0},
{sizeof(uint32_t) * DSI_TRIGGER, 0},
{sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0},
{sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0},
{sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0},
{sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0},
{sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
};
static const register_write_t display_config_dsi_01_init_06[12] = {
{sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109},
{sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14},
{sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
{sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(uint32_t) * DSI_TO_TALLY, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)},
{sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
{sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
};
static const register_write_t display_config_dsi_01_init_07[14] = {
{sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30118},
{sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14},
{sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
{sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(uint32_t) * DSI_TO_TALLY, 0},
{sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40},
{sizeof(uint32_t) * DSI_TRIGGER, 0},
{sizeof(uint32_t) * DSI_TX_CRC, 0},
{sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0},
};
static const register_write_t display_config_dsi_phy_timing_erista[1] = {
{sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070601},
};
static const register_write_t display_config_dsi_phy_timing_mariko[1] = {
{sizeof(uint32_t) * DSI_PHY_TIMING_0, 0x6070603},
};
static const dsi_sleep_or_register_write_t display_config_jdi_specific_init_01[48] = {
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0xBD15},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x1939},
{0, DSI_WR_DATA, 0xAAAAAAD8},
{0, DSI_WR_DATA, 0xAAAAAAEB},
{0, DSI_WR_DATA, 0xAAEBAAAA},
{0, DSI_WR_DATA, 0xAAAAAAAA},
{0, DSI_WR_DATA, 0xAAAAAAEB},
{0, DSI_WR_DATA, 0xAAEBAAAA},
{0, DSI_WR_DATA, 0xAA},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x1BD15},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x2739},
{0, DSI_WR_DATA, 0xFFFFFFD8},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFF},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x2BD15},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0xF39},
{0, DSI_WR_DATA, 0xFFFFFFD8},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFFFF},
{0, DSI_WR_DATA, 0xFFFFFF},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0xBD15},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x6D915},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0xB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x1105},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0xB4, 0},
{0, DSI_WR_DATA, 0x2905},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abca2_specific_init_01[14] = {
{0, DSI_WR_DATA, 0x1105},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0xB4, 0},
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0x739},
{0, DSI_WR_DATA, 0x751548B1},
{0, DSI_WR_DATA, 0x143209},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0x2905},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_init_01[14] = {
{0, DSI_WR_DATA, 0x1105},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0xB4, 0},
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0x739},
{0, DSI_WR_DATA, 0x711148B1},
{0, DSI_WR_DATA, 0x143209},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0x2905},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static const dsi_sleep_or_register_write_t display_config_innolux_auo_40_nx_abcc_specific_init_01[5] = {
{0, DSI_WR_DATA, 0x1105},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x78, 0},
{0, DSI_WR_DATA, 0x2905},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static const dsi_sleep_or_register_write_t display_config_50_nx_abcd_specific_init_01[13] = {
{0, DSI_WR_DATA, 0x1105},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0xB4, 0},
{0, DSI_WR_DATA, 0xA015},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x205315},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x339},
{0, DSI_WR_DATA, 0xFF0751},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0x2905},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static const register_write_t display_config_plld_02_erista[3] = {
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000020},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002D0AAA},
};
static const register_write_t display_config_plld_02_mariko[3] = {
{CLK_RST_CONTROLLER_PLLD_BASE, 0x4810c001},
{CLK_RST_CONTROLLER_PLLD_MISC1, 0x00000000},
{CLK_RST_CONTROLLER_PLLD_MISC, 0x002DFC00},
};
static const register_write_t display_config_dsi_01_init_08[1] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
};
static const register_write_t display_config_dsi_01_init_09[19] = {
{sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30172},
{sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14},
{sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
{sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(uint32_t) * DSI_TO_TALLY, 0},
{sizeof(uint32_t) * DSI_PKT_SEQ_0_LO, 0x40000208},
{sizeof(uint32_t) * DSI_PKT_SEQ_2_LO, 0x40000308},
{sizeof(uint32_t) * DSI_PKT_SEQ_4_LO, 0x40000308},
{sizeof(uint32_t) * DSI_PKT_SEQ_1_LO, 0x40000308},
{sizeof(uint32_t) * DSI_PKT_SEQ_3_LO, 0x3F3B2B08},
{sizeof(uint32_t) * DSI_PKT_SEQ_3_HI, 0x2CC},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_LO, 0x3F3B2B08},
{sizeof(uint32_t) * DSI_PKT_SEQ_5_HI, 0x2CC},
{sizeof(uint32_t) * DSI_PKT_LEN_0_1, 0xCE0000},
{sizeof(uint32_t) * DSI_PKT_LEN_2_3, 0x87001A2},
{sizeof(uint32_t) * DSI_PKT_LEN_4_5, 0x190},
{sizeof(uint32_t) * DSI_PKT_LEN_6_7, 0x190},
{sizeof(uint32_t) * DSI_HOST_CONTROL, 0},
};
static const register_write_t display_config_dsi_01_init_10[10] = {
{sizeof(uint32_t) * DSI_TRIGGER, 0},
{sizeof(uint32_t) * DSI_CONTROL, 0},
{sizeof(uint32_t) * DSI_SOL_DELAY, 6},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x1E0},
{sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
{sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE},
{sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}
};
static const register_write_t display_config_dsi_01_init_11_erista[4] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)},
{sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0}
};
static const register_write_t display_config_dsi_01_init_11_mariko[7] = {
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_2, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_3, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_4, 0x77777},
{sizeof(uint32_t) * DSI_PAD_CONTROL_5_MARIKO, 0x77777},
{sizeof(uint32_t) * DSI_PAD_CONTROL_6_MARIKO, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)},
{sizeof(uint32_t) * DSI_PAD_CONTROL_7_MARIKO, 0},
};
static const register_write_t display_config_mipi_cal_01[4] = {
{MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0},
{MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000},
{MIPI_CAL_MIPI_BIAS_PAD_CFG0, 1},
{MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0},
};
static const register_write_t display_config_mipi_cal_02_erista[2] = {
{MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010},
{MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0x300},
};
static const register_write_t display_config_mipi_cal_02_mariko[2] = {
{MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0x10010},
{MIPI_CAL_MIPI_BIAS_PAD_CFG1, 0},
};
static const register_write_t display_config_mipi_cal_03_erista[6] = {
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200},
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002},
{MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0},
};
static const register_write_t display_config_mipi_cal_03_mariko[6] = {
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006},
{MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000},
{MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0},
};
static const register_write_t display_config_mipi_cal_04[10] = {
{MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILD_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILE_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_CILF_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_DSIC_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0},
{MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0},
{MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0},
{MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0},
{MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001},
};
static const register_write_t display_config_dc_02[113] = {
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(uint32_t) * DC_WIN_CSC_KUR, 0},
{sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198},
{sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204},
{sizeof(uint32_t) * DC_WIN_CSC_KVB, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(uint32_t) * DC_WIN_CSC_KUR, 0},
{sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198},
{sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204},
{sizeof(uint32_t) * DC_WIN_CSC_KVB, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_DV_CONTROL, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_CSC_YOF, 0xF0},
{sizeof(uint32_t) * DC_WIN_CSC_KYRGB, 0x12A},
{sizeof(uint32_t) * DC_WIN_CSC_KUR, 0},
{sizeof(uint32_t) * DC_WIN_CSC_KVR, 0x198},
{sizeof(uint32_t) * DC_WIN_CSC_KUG, 0x39B},
{sizeof(uint32_t) * DC_WIN_CSC_KVG, 0x32F},
{sizeof(uint32_t) * DC_WIN_CSC_KUB, 0x204},
{sizeof(uint32_t) * DC_WIN_CSC_KVB, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000},
{sizeof(uint32_t) * DC_COM_PIN_OUTPUT_POLARITY(3), 0},
{sizeof(uint32_t) * DC_DISP_BLEND_BACKGROUND_COLOR, 0},
{sizeof(uint32_t) * DC_COM_CRC_CONTROL, 0},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, 0},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_TIMING_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_REF_TO_SYNC, (1 << 16)},
{sizeof(uint32_t) * DC_DISP_SYNC_WIDTH, 0x10048},
{sizeof(uint32_t) * DC_DISP_BACK_PORCH, 0x90048},
{sizeof(uint32_t) * DC_DISP_ACTIVE, 0x50002D0},
{sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
{sizeof(uint32_t) * DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE},
{sizeof(uint32_t) * DC_COM_PIN_OUTPUT_ENABLE(1), 0},
{sizeof(uint32_t) * DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL},
{sizeof(uint32_t) * DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C},
{sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX},
{sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)},
{sizeof(uint32_t) * DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND_OPTION0, 0},
};
static const register_write_t display_config_frame_buffer[32] = {
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
{sizeof(uint32_t) * DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_WIN_POSITION, 0},
{sizeof(uint32_t) * DC_WIN_H_INITIAL_DDA, 0},
{sizeof(uint32_t) * DC_WIN_V_INITIAL_DDA, 0},
{sizeof(uint32_t) * DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(2880)},
{sizeof(uint32_t) * DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)},
{sizeof(uint32_t) * DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)},
{sizeof(uint32_t) * DC_WIN_LINE_STRIDE, 0x6000C00},
{sizeof(uint32_t) * DC_WIN_BUFFER_CONTROL, 0},
{sizeof(uint32_t) * DC_WINBUF_SURFACE_KIND, 0},
{sizeof(uint32_t) * DC_WINBUF_START_ADDR, display_config_frame_buffer_address},
{sizeof(uint32_t) * DC_WINBUF_ADDR_H_OFFSET, 0},
{sizeof(uint32_t) * DC_WINBUF_ADDR_V_OFFSET, 0},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, WIN_ENABLE},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ},
};
static const register_write_t display_config_solid_color[8] = {
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
{sizeof(uint32_t) * DC_WIN_WIN_OPTIONS, 0},
{sizeof(uint32_t) * DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY},
};
static const register_write_t display_config_dc_01_fini_01[13] = {
{sizeof(uint32_t) * DC_DISP_FRONT_PORCH, 0xA0088},
{sizeof(uint32_t) * DC_CMD_INT_MASK, 0},
{sizeof(uint32_t) * DC_CMD_STATE_ACCESS, 0},
{sizeof(uint32_t) * DC_CMD_INT_ENABLE, 0},
{sizeof(uint32_t) * DC_CMD_CONT_SYNCPT_VSYNC, 0},
{sizeof(uint32_t) * DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{sizeof(uint32_t) * DC_CMD_GENERAL_INCR_SYNCPT, 0x301},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
{sizeof(uint32_t) * DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
};
static const register_write_t display_config_dsi_01_fini_01[2] = {
{sizeof(uint32_t) * DSI_POWER_CONTROL, 0},
{sizeof(uint32_t) * DSI_PAD_CONTROL_1, 0},
};
static const register_write_t display_config_dsi_01_fini_02[13] = {
{sizeof(uint32_t) * DSI_PHY_TIMING_1, 0x40A0E05},
{sizeof(uint32_t) * DSI_PHY_TIMING_2, 0x30109},
{sizeof(uint32_t) * DSI_BTA_TIMING, 0x190A14},
{sizeof(uint32_t) * DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) },
{sizeof(uint32_t) * DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
{sizeof(uint32_t) * DSI_TO_TALLY, 0},
{sizeof(uint32_t) * DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
{sizeof(uint32_t) * DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
{sizeof(uint32_t) * DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
{sizeof(uint32_t) * DSI_MAX_THRESHOLD, 0x40},
{sizeof(uint32_t) * DSI_TRIGGER, 0},
{sizeof(uint32_t) * DSI_TX_CRC, 0},
{sizeof(uint32_t) * DSI_INIT_SEQ_CONTROL, 0}
};
static const dsi_sleep_or_register_write_t display_config_jdi_specific_fini_01[22] = {
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x2139},
{0, DSI_WR_DATA, 0x191919D5},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0xB39},
{0, DSI_WR_DATA, 0x4F0F41B1},
{0, DSI_WR_DATA, 0xF179A433},
{0, DSI_WR_DATA, 0x2D81},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0xB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
};
static const dsi_sleep_or_register_write_t display_config_auo_nx_abca2_specific_fini_01[38] = {
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x2C39},
{0, DSI_WR_DATA, 0x191919D5},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x2C39},
{0, DSI_WR_DATA, 0x191919D6},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_WR_DATA, 0x19191919},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0xB39},
{0, DSI_WR_DATA, 0x711148B1},
{0, DSI_WR_DATA, 0x71143209},
{0, DSI_WR_DATA, 0x114D31},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0xB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
};
static const dsi_sleep_or_register_write_t display_config_innolux_nx_abcc_specific_fini_01[10] = {
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0xB39},
{0, DSI_WR_DATA, 0x751548B1},
{0, DSI_WR_DATA, 0x71143209},
{0, DSI_WR_DATA, 0x115631},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
};
static const dsi_sleep_or_register_write_t display_config_auo_nx_abcc_specific_fini_01[10] = {
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0xB39},
{0, DSI_WR_DATA, 0x711148B1},
{0, DSI_WR_DATA, 0x71143209},
{0, DSI_WR_DATA, 0x114D31},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
};
static const dsi_sleep_or_register_write_t display_config_40_nx_abcc_specific_fini_01[10] = {
{0, DSI_WR_DATA, 0x439},
{0, DSI_WR_DATA, 0x9483FFB9},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
{0, DSI_WR_DATA, 0xB39},
{0, DSI_WR_DATA, 0x731348B1},
{0, DSI_WR_DATA, 0x71243209},
{0, DSI_WR_DATA, 0x4C31},
{0, DSI_TRIGGER, DSI_TRIGGER_HOST},
{1, 0x5, 0},
};

2218
fusee/fusee-primary/src/emc.h → fusee/fusee-primary/fusee-primary-main/src/emc.h
View file

File diff suppressed because it is too large Load diff

4
fusee/fusee-primary/src/exception_handlers.c → fusee/fusee-primary/fusee-primary-main/src/exception_handlers.c
View file

@ -18,8 +18,8 @@
#include "exception_handlers.h"
#include "utils.h"
#include "lib/log.h"
#include "lib/vsprintf.h"
#include "../../../fusee/common/log.h"
#include "../../../fusee/common/vsprintf.h"
#define CODE_DUMP_SIZE 0x30
#define STACK_DUMP_SIZE 0x30

0
fusee/fusee-primary/src/exception_handlers.h → fusee/fusee-primary/fusee-primary-main/src/exception_handlers.h
View file

0
fusee/fusee-primary/src/exception_handlers_asm.s → fusee/fusee-primary/fusee-primary-main/src/exception_handlers_asm.s
View file

0
fusee/fusee-primary/src/flow.h → fusee/fusee-primary/fusee-primary-main/src/flow.h
View file

6
fusee/fusee-primary/src/fs_utils.c → fusee/fusee-primary/fusee-primary-main/src/fs_utils.c
View file

@ -16,8 +16,8 @@
#include "fs_utils.h"
#include "mc.h"
#include "lib/fatfs/ff.h"
#include "lib/log.h"
#include "../../../fusee/common/fatfs/ff.h"
#include "../../../fusee/common/log.h"
FATFS sd_fs;
static bool g_sd_mounted = false;
@ -41,7 +41,7 @@ bool mount_sd(void)
if (!g_sd_initialized) {
/* Initialize SD. */
if (sdmmc_device_sd_init(&g_sd_device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_UHS_SDR104))
if (sdmmc_device_sd_init(&g_sd_device, &g_sd_sdmmc, SDMMC_BUS_WIDTH_4BIT, SDMMC_SPEED_SD_SDR104))
{
g_sd_initialized = true;

2
fusee/fusee-primary/src/fs_utils.h → fusee/fusee-primary/fusee-primary-main/src/fs_utils.h
View file

@ -20,7 +20,7 @@
#include <stdbool.h>
#include <stdint.h>
#include "sdmmc/sdmmc.h"
#include "../../../fusee/common/sdmmc/sdmmc.h"
#include "utils.h"
extern sdmmc_t g_sd_sdmmc;

199
fusee/fusee-primary/src/fuse.c → fusee/fusee-primary/fusee-primary-main/src/fuse.c
View file

@ -24,11 +24,6 @@
#include "pmc.h"
#include "timers.h"
/* Prototypes for internal commands. */
void fuse_enable_power(void);
void fuse_disable_power(void);
void fuse_wait_idle(void);
/* Initialize the fuse driver */
void fuse_init(void) {
/* Make all fuse registers visible, disable the private key and disable programming. */
@ -43,7 +38,7 @@ void fuse_disable_private_key(void) {
fuse->FUSE_PRIVATEKEYDISABLE = 0x10;
}
/* Disables all fuse programming. */
/* Disable all fuse programming. */
void fuse_disable_programming(void) {
volatile tegra_fuse_t *fuse = fuse_get_regs();
fuse->FUSE_DISABLEREGPROGRAM = 1;
@ -68,13 +63,14 @@ void fuse_disable_power(void) {
}
/* Wait for the fuse driver to go idle. */
void fuse_wait_idle(void) {
static void fuse_wait_idle(void) {
volatile tegra_fuse_t *fuse = fuse_get_regs();
uint32_t ctrl_val = 0;
/* Wait for STATE_IDLE */
while ((ctrl_val & (0xF0000)) != 0x40000)
while ((ctrl_val & (0xF0000)) != 0x40000) {
ctrl_val = fuse->FUSE_FUSECTRL;
}
}
/* Read a fuse from the hardware array. */
@ -120,7 +116,7 @@ void fuse_hw_write(uint32_t value, uint32_t addr) {
fuse_wait_idle();
}
/* Sense the fuse hardware array into the shadow cache. */
/* Sense the fuse hardware array into the fuse cache. */
void fuse_hw_sense(void) {
volatile tegra_fuse_t *fuse = fuse_get_regs();
@ -137,46 +133,68 @@ void fuse_hw_sense(void) {
fuse_wait_idle();
}
/* Read the SKU info register from the shadow cache. */
/* Read the SKU info register. */
uint32_t fuse_get_sku_info(void) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
return fuse_chip->FUSE_SKU_INFO;
}
/* Read the bootrom patch version from a register in the shadow cache. */
/* Read the bootrom patch version. */
uint32_t fuse_get_bootrom_patch_version(void) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
return fuse_chip->FUSE_SOC_SPEEDO_1_CALIB;
}
/* Read a spare bit register from the shadow cache */
uint32_t fuse_get_spare_bit(uint32_t idx) {
if (idx < 32) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
return fuse_chip->FUSE_SPARE_BIT[idx];
} else {
return 0;
/* Read a spare bit register. */
uint32_t fuse_get_spare_bit(uint32_t index) {
uint32_t soc_type = fuse_get_soc_type();
if (soc_type == 0) {
if (index < 32) {
volatile tegra_fuse_chip_erista_t *fuse_chip = fuse_chip_erista_get_regs();
return fuse_chip->FUSE_SPARE_BIT[index];
}
} else if (soc_type == 1) {
if (index < 30) {
volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
return fuse_chip->FUSE_SPARE_BIT[index];
}
}
return 0;
}
/* Read a reserved ODM register from the shadow cache. */
uint32_t fuse_get_reserved_odm(uint32_t idx) {
if (idx < 8) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
return fuse_chip->FUSE_RESERVED_ODM[idx];
/* Read a reserved ODM register. */
uint32_t fuse_get_reserved_odm(uint32_t index) {
if (index < 8) {
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
return fuse_chip->FUSE_RESERVED_ODM0[index];
} else {
return 0;
uint32_t soc_type = fuse_get_soc_type();
if (soc_type == 1) {
volatile tegra_fuse_chip_mariko_t *fuse_chip = fuse_chip_mariko_get_regs();
if (index < 22) {
return fuse_chip->FUSE_RESERVED_ODM8[index - 8];
} else if (index < 25) {
return fuse_chip->FUSE_RESERVED_ODM22[index - 22];
} else if (index < 26) {
return fuse_chip->FUSE_RESERVED_ODM25;
} else if (index < 29) {
return fuse_chip->FUSE_RESERVED_ODM26[index - 26];
} else if (index < 30) {
return fuse_chip->FUSE_RESERVED_ODM29;
}
}
}
return 0;
}
/* Get the DRAM ID using values in the shadow cache. */
/* Get the DramId. */
uint32_t fuse_get_dram_id(void) {
return ((fuse_get_reserved_odm(4) >> 3) & 0x7);
return ((fuse_get_reserved_odm(4) >> 3) & 0x1F);
}
/* Derive the Device ID using values in the shadow cache. */
/* Derive the DeviceId. */
uint64_t fuse_get_device_id(void) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
uint64_t device_id = 0;
uint64_t y_coord = fuse_chip->FUSE_OPT_Y_COORDINATE & 0x1FF;
@ -200,48 +218,74 @@ uint64_t fuse_get_device_id(void) {
return device_id;
}
/* Derive the Hardware Type using values in the shadow cache. */
uint32_t fuse_get_hardware_type(uint32_t target_firmware) {
/* Derive the HardwareType with firmware specific checks. */
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware) {
uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
uint32_t hardware_type = (((fuse_reserved_odm4 >> 7) & 2) | ((fuse_reserved_odm4 >> 2) & 1));
/* Firmware from versions 1.0.0 to 3.0.2. */
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_4_0_0) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
if (hardware_type >= 1) {
return (hardware_type > 2) ? 3 : hardware_type - 1;
} else if ((fuse_chip->FUSE_SPARE_BIT[9] & 1) == 0) {
return 0;
} else {
return 3;
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
uint32_t fuse_spare_bit9 = (fuse_chip->FUSE_SPARE_BIT[9] & 1);
switch (hardware_type) {
case 0x00: return (fuse_spare_bit9 == 0) ? 0 : 3;
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 1; /* HardwareType_Copper */
default: return 3; /* HardwareType_Undefined */
}
} else if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) { /* Firmware versions from 4.0.0 to 6.2.0. */
static const uint32_t types[] = {0,1,4,3};
} else {
hardware_type |= ((fuse_reserved_odm4 >> 14) & 0x3C);
hardware_type--;
return (hardware_type > 3) ? 4 : types[hardware_type];
} else { /* Firmware versions from 7.0.0 onwards. */
/* Always return 0 in retail. */
return 0;
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_7_0_0) {
switch (hardware_type) {
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 1; /* HardwareType_Copper */
case 0x04: return 3; /* HardwareType_Iowa */
default: return 4; /* HardwareType_Undefined */
}
} else {
if (target_firmware < ATMOSPHERE_TARGET_FIRMWARE_10_0_0) {
switch (hardware_type) {
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 4; /* HardwareType_Calcio */
case 0x04: return 3; /* HardwareType_Iowa */
case 0x08: return 2; /* HardwareType_Hoag */
default: return 0xF; /* HardwareType_Undefined */
}
} else {
switch (hardware_type) {
case 0x01: return 0; /* HardwareType_Icosa */
case 0x02: return 4; /* HardwareType_Calcio */
case 0x04: return 3; /* HardwareType_Iowa */
case 0x08: return 2; /* HardwareType_Hoag */
case 0x10: return 5; /* HardwareType_Five */
default: return 0xF; /* HardwareType_Undefined */
}
}
}
}
}
/* Derive the Retail Type using values in the shadow cache. */
uint32_t fuse_get_retail_type(void) {
/* Retail Type = IS_RETAIL | UNIT_TYPE. */
/* Derive the HardwareType. */
uint32_t fuse_get_hardware_type(void) {
return fuse_get_hardware_type_with_firmware_check(ATMOSPHERE_TARGET_FIRMWARE_CURRENT);
}
/* Derive the HardwareState. */
uint32_t fuse_get_hardware_state(void) {
uint32_t fuse_reserved_odm4 = fuse_get_reserved_odm(4);
uint32_t retail_type = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
if (retail_type == 4) { /* Standard retail unit, IS_RETAIL | 0. */
return 1;
} else if (retail_type == 3) { /* Standard dev unit, 0 | DEV_UNIT. */
return 0;
uint32_t hardware_state = (((fuse_reserved_odm4 >> 7) & 4) | (fuse_reserved_odm4 & 3));
switch (hardware_state) {
case 0x03: return 0; /* HardwareState_Development */
case 0x04: return 1; /* HardwareState_Production */
default: return 2; /* HardwareState_Undefined */
}
return 2; /* IS_RETAIL | DEV_UNIT */
}
/* Derive the 16-byte Hardware Info using values in the shadow cache, and copy to output buffer. */
/* Derive the 16-byte HardwareInfo and copy to output buffer. */
void fuse_get_hardware_info(void *dst) {
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
uint32_t hw_info[0x4];
uint32_t ops_reserved = fuse_chip->FUSE_OPT_OPS_RESERVED & 0x3F;
@ -261,3 +305,42 @@ void fuse_get_hardware_info(void *dst) {
memcpy(dst, hw_info, 0x10);
}
/* Check if have a new ODM fuse format. */
bool fuse_is_new_format(void) {
return ((fuse_get_reserved_odm(4) & 0x800) && (fuse_get_reserved_odm(0) == 0x8E61ECAE) && (fuse_get_reserved_odm(1) == 0xF2BA3BB2));
}
/* Get the DeviceUniqueKeyGeneration. */
uint32_t fuse_get_device_unique_key_generation(void) {
if (fuse_is_new_format()) {
return (fuse_get_reserved_odm(2) & 0x1F);
} else {
return 0;
}
}
/* Get the SocType from the HardwareType. */
uint32_t fuse_get_soc_type(void) {
switch (fuse_get_hardware_type()) {
case 0:
case 1:
return 0; /* SocType_Erista */
case 3:
case 2:
case 4:
case 5:
return 1; /* SocType_Mariko */
default:
return 0xF; /* SocType_Undefined */
}
}
/* Get the Regulator type. */
uint32_t fuse_get_regulator(void) {
if (fuse_get_soc_type() == 1) {
return ((fuse_get_reserved_odm(28) & 1) + 1); /* Regulator_Mariko_Max77812_A or Regulator_Mariko_Max77812_B */
} else {
return 0; /* Regulator_Erista_Max77621 */
}
}

484
fusee/fusee-primary/fusee-primary-main/src/fuse.h Normal file
View file

@ -0,0 +1,484 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_FUSE_H
#define FUSEE_FUSE_H
#define FUSE_BASE 0x7000F800
#define FUSE_CHIP_BASE (FUSE_BASE + 0x98)
#define MAKE_FUSE_REG(n) MAKE_REG32(FUSE_BASE + n)
#define MAKE_FUSE_CHIP_REG(n) MAKE_REG32(FUSE_CHIP_BASE + n)
typedef struct {
uint32_t FUSE_FUSECTRL;
uint32_t FUSE_FUSEADDR;
uint32_t FUSE_FUSERDATA;
uint32_t FUSE_FUSEWDATA;
uint32_t FUSE_FUSETIME_RD1;
uint32_t FUSE_FUSETIME_RD2;
uint32_t FUSE_FUSETIME_PGM1;
uint32_t FUSE_FUSETIME_PGM2;
uint32_t FUSE_PRIV2INTFC_START;
uint32_t FUSE_FUSEBYPASS;
uint32_t FUSE_PRIVATEKEYDISABLE;
uint32_t FUSE_DISABLEREGPROGRAM;
uint32_t FUSE_WRITE_ACCESS_SW;
uint32_t FUSE_PWR_GOOD_SW;
uint32_t _0x38;
uint32_t FUSE_PRIV2RESHIFT;
uint32_t _0x40[0x3];
uint32_t FUSE_FUSETIME_RD3;
uint32_t _0x50[0xC];
uint32_t FUSE_PRIVATE_KEY0_NONZERO;
uint32_t FUSE_PRIVATE_KEY1_NONZERO;
uint32_t FUSE_PRIVATE_KEY2_NONZERO;
uint32_t FUSE_PRIVATE_KEY3_NONZERO;
uint32_t FUSE_PRIVATE_KEY4_NONZERO;
uint32_t _0x94;
} tegra_fuse_t;
typedef struct {
uint32_t _0x98[0x1A];
uint32_t FUSE_PRODUCTION_MODE;
uint32_t FUSE_JTAG_SECUREID_VALID;
uint32_t FUSE_ODM_LOCK;
uint32_t FUSE_OPT_OPENGL_EN;
uint32_t FUSE_SKU_INFO;
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
uint32_t FUSE_CPU_IDDQ_CALIB;
uint32_t _0x11C[0x3];
uint32_t FUSE_OPT_FT_REV;
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_IDDQ_CALIB;
uint32_t _0x144;
uint32_t FUSE_FA;
uint32_t FUSE_RESERVED_PRODUCTION;
uint32_t FUSE_HDMI_LANE0_CALIB;
uint32_t FUSE_HDMI_LANE1_CALIB;
uint32_t FUSE_HDMI_LANE2_CALIB;
uint32_t FUSE_HDMI_LANE3_CALIB;
uint32_t FUSE_ENCRYPTION_RATE;
uint32_t FUSE_PUBLIC_KEY[0x8];
uint32_t FUSE_TSENSOR1_CALIB;
uint32_t FUSE_TSENSOR2_CALIB;
uint32_t _0x18C;
uint32_t FUSE_OPT_CP_REV;
uint32_t FUSE_OPT_PFG;
uint32_t FUSE_TSENSOR0_CALIB;
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
uint32_t FUSE_SECURITY_MODE;
uint32_t FUSE_PRIVATE_KEY[0x5];
uint32_t FUSE_ARM_JTAG_DIS;
uint32_t FUSE_BOOT_DEVICE_INFO;
uint32_t FUSE_RESERVED_SW;
uint32_t FUSE_OPT_VP9_DISABLE;
uint32_t FUSE_RESERVED_ODM0[0x8];
uint32_t FUSE_OBS_DIS;
uint32_t _0x1EC;
uint32_t FUSE_USB_CALIB;
uint32_t FUSE_SKU_DIRECT_CONFIG;
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
uint32_t FUSE_PACKAGE_INFO;
uint32_t FUSE_OPT_VENDOR_CODE;
uint32_t FUSE_OPT_FAB_CODE;
uint32_t FUSE_OPT_LOT_CODE_0;
uint32_t FUSE_OPT_LOT_CODE_1;
uint32_t FUSE_OPT_WAFER_ID;
uint32_t FUSE_OPT_X_COORDINATE;
uint32_t FUSE_OPT_Y_COORDINATE;
uint32_t FUSE_OPT_SEC_DEBUG_EN;
uint32_t FUSE_OPT_OPS_RESERVED;
uint32_t _0x224;
uint32_t FUSE_GPU_IDDQ_CALIB;
uint32_t FUSE_TSENSOR3_CALIB;
uint32_t FUSE_CLOCK_BOUNDOUT0;
uint32_t FUSE_CLOCK_BOUNDOUT1;
uint32_t _0x238[0x3];
uint32_t FUSE_OPT_SAMPLE_TYPE;
uint32_t FUSE_OPT_SUBREVISION;
uint32_t FUSE_OPT_SW_RESERVED_0;
uint32_t FUSE_OPT_SW_RESERVED_1;
uint32_t FUSE_TSENSOR4_CALIB;
uint32_t FUSE_TSENSOR5_CALIB;
uint32_t FUSE_TSENSOR6_CALIB;
uint32_t FUSE_TSENSOR7_CALIB;
uint32_t FUSE_OPT_PRIV_SEC_EN;
uint32_t _0x268[0x5];
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
uint32_t FUSE_TSENSOR_COMMON;
uint32_t FUSE_OPT_CP_BIN;
uint32_t FUSE_OPT_GPU_DISABLE;
uint32_t FUSE_OPT_FT_BIN;
uint32_t FUSE_OPT_DONE_MAP;
uint32_t _0x294;
uint32_t FUSE_APB2JTAG_DISABLE;
uint32_t FUSE_ODM_INFO;
uint32_t _0x2A0[0x2];
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
uint32_t _0x2AC[0x5];
uint32_t FUSE_WOA_SKU_FLAG;
uint32_t FUSE_ECO_RESERVE_1;
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
uint32_t FUSE_PRODUCTION_MONTH;
uint32_t FUSE_RAM_REPAIR_INDICATOR;
uint32_t FUSE_TSENSOR9_CALIB;
uint32_t _0x2D8;
uint32_t FUSE_VMIN_CALIBRATION;
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
uint32_t FUSE_DEBUG_AUTHENTICATION;
uint32_t FUSE_SECURE_PROVISION_INDEX;
uint32_t FUSE_SECURE_PROVISION_INFO;
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
uint32_t FUSE_SPARE_ENDIS;
uint32_t FUSE_ECO_RESERVE_0;
uint32_t _0x2FC[0x2];
uint32_t FUSE_RESERVED_CALIB0;
uint32_t FUSE_RESERVED_CALIB1;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
uint32_t FUSE_OPT_CPU_DISABLE;
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
uint32_t FUSE_TSENSOR10_CALIB;
uint32_t FUSE_TSENSOR10_CALIB_AUX;
uint32_t _0x324[0x5];
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
uint32_t FUSE_USB_CALIB_EXT;
uint32_t FUSE_RESERVED_FIELD;
uint32_t _0x358[0x9];
uint32_t FUSE_SPARE_REALIGNMENT_REG;
uint32_t FUSE_SPARE_BIT[0x20];
} tegra_fuse_chip_common_t;
typedef struct {
uint32_t _0x98[0x1A];
uint32_t FUSE_PRODUCTION_MODE;
uint32_t FUSE_JTAG_SECUREID_VALID;
uint32_t FUSE_ODM_LOCK;
uint32_t FUSE_OPT_OPENGL_EN;
uint32_t FUSE_SKU_INFO;
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
uint32_t FUSE_CPU_IDDQ_CALIB;
uint32_t _0x11C[0x3];
uint32_t FUSE_OPT_FT_REV;
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_IDDQ_CALIB;
uint32_t _0x144;
uint32_t FUSE_FA;
uint32_t FUSE_RESERVED_PRODUCTION;
uint32_t FUSE_HDMI_LANE0_CALIB;
uint32_t FUSE_HDMI_LANE1_CALIB;
uint32_t FUSE_HDMI_LANE2_CALIB;
uint32_t FUSE_HDMI_LANE3_CALIB;
uint32_t FUSE_ENCRYPTION_RATE;
uint32_t FUSE_PUBLIC_KEY[0x8];
uint32_t FUSE_TSENSOR1_CALIB;
uint32_t FUSE_TSENSOR2_CALIB;
uint32_t _0x18C;
uint32_t FUSE_OPT_CP_REV;
uint32_t FUSE_OPT_PFG;
uint32_t FUSE_TSENSOR0_CALIB;
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
uint32_t FUSE_SECURITY_MODE;
uint32_t FUSE_PRIVATE_KEY[0x5];
uint32_t FUSE_ARM_JTAG_DIS;
uint32_t FUSE_BOOT_DEVICE_INFO;
uint32_t FUSE_RESERVED_SW;
uint32_t FUSE_OPT_VP9_DISABLE;
uint32_t FUSE_RESERVED_ODM0[0x8];
uint32_t FUSE_OBS_DIS;
uint32_t _0x1EC;
uint32_t FUSE_USB_CALIB;
uint32_t FUSE_SKU_DIRECT_CONFIG;
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
uint32_t FUSE_PACKAGE_INFO;
uint32_t FUSE_OPT_VENDOR_CODE;
uint32_t FUSE_OPT_FAB_CODE;
uint32_t FUSE_OPT_LOT_CODE_0;
uint32_t FUSE_OPT_LOT_CODE_1;
uint32_t FUSE_OPT_WAFER_ID;
uint32_t FUSE_OPT_X_COORDINATE;
uint32_t FUSE_OPT_Y_COORDINATE;
uint32_t FUSE_OPT_SEC_DEBUG_EN;
uint32_t FUSE_OPT_OPS_RESERVED;
uint32_t FUSE_SATA_CALIB; /* Erista only. */
uint32_t FUSE_GPU_IDDQ_CALIB;
uint32_t FUSE_TSENSOR3_CALIB;
uint32_t FUSE_CLOCK_BOUNDOUT0;
uint32_t FUSE_CLOCK_BOUNDOUT1;
uint32_t _0x238[0x3];
uint32_t FUSE_OPT_SAMPLE_TYPE;
uint32_t FUSE_OPT_SUBREVISION;
uint32_t FUSE_OPT_SW_RESERVED_0;
uint32_t FUSE_OPT_SW_RESERVED_1;
uint32_t FUSE_TSENSOR4_CALIB;
uint32_t FUSE_TSENSOR5_CALIB;
uint32_t FUSE_TSENSOR6_CALIB;
uint32_t FUSE_TSENSOR7_CALIB;
uint32_t FUSE_OPT_PRIV_SEC_EN;
uint32_t FUSE_PKC_DISABLE; /* Erista only. */
uint32_t _0x26C[0x4];
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
uint32_t FUSE_TSENSOR_COMMON;
uint32_t FUSE_OPT_CP_BIN;
uint32_t FUSE_OPT_GPU_DISABLE;
uint32_t FUSE_OPT_FT_BIN;
uint32_t FUSE_OPT_DONE_MAP;
uint32_t _0x294;
uint32_t FUSE_APB2JTAG_DISABLE;
uint32_t FUSE_ODM_INFO;
uint32_t _0x2A0[0x2];
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
uint32_t _0x2AC[0x5];
uint32_t FUSE_WOA_SKU_FLAG;
uint32_t FUSE_ECO_RESERVE_1;
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
uint32_t FUSE_PRODUCTION_MONTH;
uint32_t FUSE_RAM_REPAIR_INDICATOR;
uint32_t FUSE_TSENSOR9_CALIB;
uint32_t _0x2D8;
uint32_t FUSE_VMIN_CALIBRATION;
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
uint32_t FUSE_DEBUG_AUTHENTICATION;
uint32_t FUSE_SECURE_PROVISION_INDEX;
uint32_t FUSE_SECURE_PROVISION_INFO;
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
uint32_t FUSE_SPARE_ENDIS;
uint32_t FUSE_ECO_RESERVE_0;
uint32_t _0x2FC[0x2];
uint32_t FUSE_RESERVED_CALIB0;
uint32_t FUSE_RESERVED_CALIB1;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
uint32_t FUSE_OPT_CPU_DISABLE;
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
uint32_t FUSE_TSENSOR10_CALIB;
uint32_t FUSE_TSENSOR10_CALIB_AUX;
uint32_t FUSE_OPT_RAM_SVOP_DP; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_PDP; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_REG; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_SP; /* Erista only. */
uint32_t FUSE_OPT_RAM_SVOP_SMPDP; /* Erista only. */
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
uint32_t FUSE_USB_CALIB_EXT;
uint32_t FUSE_RESERVED_FIELD;
uint32_t _0x358[0x9];
uint32_t FUSE_SPARE_REALIGNMENT_REG;
uint32_t FUSE_SPARE_BIT[0x20];
} tegra_fuse_chip_erista_t;
typedef struct {
uint32_t FUSE_RESERVED_ODM8[0xE]; /* Mariko only. */
uint32_t FUSE_KEK[0x4]; /* Mariko only. */
uint32_t FUSE_BEK[0x4]; /* Mariko only. */
uint32_t _0xF0; /* Mariko only. */
uint32_t _0xF4; /* Mariko only. */
uint32_t _0xF8; /* Mariko only. */
uint32_t _0xFC; /* Mariko only. */
uint32_t FUSE_PRODUCTION_MODE;
uint32_t FUSE_JTAG_SECUREID_VALID;
uint32_t FUSE_ODM_LOCK;
uint32_t FUSE_OPT_OPENGL_EN;
uint32_t FUSE_SKU_INFO;
uint32_t FUSE_CPU_SPEEDO_0_CALIB;
uint32_t FUSE_CPU_IDDQ_CALIB;
uint32_t FUSE_RESERVED_ODM22[0x3]; /* Mariko only. */
uint32_t FUSE_OPT_FT_REV;
uint32_t FUSE_CPU_SPEEDO_1_CALIB;
uint32_t FUSE_CPU_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_SPEEDO_0_CALIB;
uint32_t FUSE_SOC_SPEEDO_1_CALIB;
uint32_t FUSE_SOC_SPEEDO_2_CALIB;
uint32_t FUSE_SOC_IDDQ_CALIB;
uint32_t FUSE_RESERVED_ODM25; /* Mariko only. */
uint32_t FUSE_FA;
uint32_t FUSE_RESERVED_PRODUCTION;
uint32_t FUSE_HDMI_LANE0_CALIB;
uint32_t FUSE_HDMI_LANE1_CALIB;
uint32_t FUSE_HDMI_LANE2_CALIB;
uint32_t FUSE_HDMI_LANE3_CALIB;
uint32_t FUSE_ENCRYPTION_RATE;
uint32_t FUSE_PUBLIC_KEY[0x8];
uint32_t FUSE_TSENSOR1_CALIB;
uint32_t FUSE_TSENSOR2_CALIB;
uint32_t FUSE_OPT_SECURE_SCC_DIS; /* Mariko only. */
uint32_t FUSE_OPT_CP_REV;
uint32_t FUSE_OPT_PFG;
uint32_t FUSE_TSENSOR0_CALIB;
uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE;
uint32_t FUSE_SECURITY_MODE;
uint32_t FUSE_PRIVATE_KEY[0x5];
uint32_t FUSE_ARM_JTAG_DIS;
uint32_t FUSE_BOOT_DEVICE_INFO;
uint32_t FUSE_RESERVED_SW;
uint32_t FUSE_OPT_VP9_DISABLE;
uint32_t FUSE_RESERVED_ODM0[0x8];
uint32_t FUSE_OBS_DIS;
uint32_t _0x1EC; /* Mariko only. */
uint32_t FUSE_USB_CALIB;
uint32_t FUSE_SKU_DIRECT_CONFIG;
uint32_t FUSE_KFUSE_PRIVKEY_CTRL;
uint32_t FUSE_PACKAGE_INFO;
uint32_t FUSE_OPT_VENDOR_CODE;
uint32_t FUSE_OPT_FAB_CODE;
uint32_t FUSE_OPT_LOT_CODE_0;
uint32_t FUSE_OPT_LOT_CODE_1;
uint32_t FUSE_OPT_WAFER_ID;
uint32_t FUSE_OPT_X_COORDINATE;
uint32_t FUSE_OPT_Y_COORDINATE;
uint32_t FUSE_OPT_SEC_DEBUG_EN;
uint32_t FUSE_OPT_OPS_RESERVED;
uint32_t _0x224; /* Mariko only. */
uint32_t FUSE_GPU_IDDQ_CALIB;
uint32_t FUSE_TSENSOR3_CALIB;
uint32_t FUSE_CLOCK_BOUNDOUT0;
uint32_t FUSE_CLOCK_BOUNDOUT1;
uint32_t FUSE_RESERVED_ODM26[0x3]; /* Mariko only. */
uint32_t FUSE_OPT_SAMPLE_TYPE;
uint32_t FUSE_OPT_SUBREVISION;
uint32_t FUSE_OPT_SW_RESERVED_0;
uint32_t FUSE_OPT_SW_RESERVED_1;
uint32_t FUSE_TSENSOR4_CALIB;
uint32_t FUSE_TSENSOR5_CALIB;
uint32_t FUSE_TSENSOR6_CALIB;
uint32_t FUSE_TSENSOR7_CALIB;
uint32_t FUSE_OPT_PRIV_SEC_EN;
uint32_t FUSE_BOOT_SECURITY_INFO; /* Mariko only. */
uint32_t _0x26C; /* Mariko only. */
uint32_t _0x270; /* Mariko only. */
uint32_t _0x274; /* Mariko only. */
uint32_t _0x278; /* Mariko only. */
uint32_t FUSE_FUSE2TSEC_DEBUG_DISABLE;
uint32_t FUSE_TSENSOR_COMMON;
uint32_t FUSE_OPT_CP_BIN;
uint32_t FUSE_OPT_GPU_DISABLE;
uint32_t FUSE_OPT_FT_BIN;
uint32_t FUSE_OPT_DONE_MAP;
uint32_t FUSE_RESERVED_ODM29; /* Mariko only. */
uint32_t FUSE_APB2JTAG_DISABLE;
uint32_t FUSE_ODM_INFO;
uint32_t _0x2A0[0x2];
uint32_t FUSE_ARM_CRYPT_DE_FEATURE;
uint32_t _0x2AC;
uint32_t _0x2B0; /* Mariko only. */
uint32_t _0x2B4; /* Mariko only. */
uint32_t _0x2B8; /* Mariko only. */
uint32_t _0x2BC; /* Mariko only. */
uint32_t FUSE_WOA_SKU_FLAG;
uint32_t FUSE_ECO_RESERVE_1;
uint32_t FUSE_GCPLEX_CONFIG_FUSE;
uint32_t FUSE_PRODUCTION_MONTH;
uint32_t FUSE_RAM_REPAIR_INDICATOR;
uint32_t FUSE_TSENSOR9_CALIB;
uint32_t _0x2D8;
uint32_t FUSE_VMIN_CALIBRATION;
uint32_t FUSE_AGING_SENSOR_CALIBRATION;
uint32_t FUSE_DEBUG_AUTHENTICATION;
uint32_t FUSE_SECURE_PROVISION_INDEX;
uint32_t FUSE_SECURE_PROVISION_INFO;
uint32_t FUSE_OPT_GPU_DISABLE_CP1;
uint32_t FUSE_SPARE_ENDIS;
uint32_t FUSE_ECO_RESERVE_0;
uint32_t _0x2FC[0x2];
uint32_t FUSE_RESERVED_CALIB0;
uint32_t FUSE_RESERVED_CALIB1;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE;
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP1;
uint32_t FUSE_OPT_CPU_DISABLE;
uint32_t FUSE_OPT_CPU_DISABLE_CP1;
uint32_t FUSE_TSENSOR10_CALIB;
uint32_t FUSE_TSENSOR10_CALIB_AUX;
uint32_t _0x324; /* Mariko only. */
uint32_t _0x328; /* Mariko only. */
uint32_t _0x32C; /* Mariko only. */
uint32_t _0x330; /* Mariko only. */
uint32_t _0x334; /* Mariko only. */
uint32_t FUSE_OPT_GPU_TPC0_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP1;
uint32_t FUSE_OPT_GPU_TPC1_DISABLE_CP2;
uint32_t FUSE_OPT_CPU_DISABLE_CP2;
uint32_t FUSE_OPT_GPU_DISABLE_CP2;
uint32_t FUSE_USB_CALIB_EXT;
uint32_t FUSE_RESERVED_FIELD;
uint32_t _0x358[0x9];
uint32_t FUSE_SPARE_REALIGNMENT_REG;
uint32_t FUSE_SPARE_BIT[0x1E];
} tegra_fuse_chip_mariko_t;
static inline volatile tegra_fuse_t *fuse_get_regs(void)
{
return (volatile tegra_fuse_t *)FUSE_BASE;
}
static inline volatile tegra_fuse_chip_common_t *fuse_chip_common_get_regs(void)
{
return (volatile tegra_fuse_chip_common_t *)FUSE_CHIP_BASE;
}
static inline volatile tegra_fuse_chip_erista_t *fuse_chip_erista_get_regs(void)
{
return (volatile tegra_fuse_chip_erista_t *)FUSE_CHIP_BASE;
}
static inline volatile tegra_fuse_chip_mariko_t *fuse_chip_mariko_get_regs(void)
{
return (volatile tegra_fuse_chip_mariko_t *)FUSE_CHIP_BASE;
}
void fuse_init(void);
void fuse_disable_programming(void);
void fuse_disable_private_key(void);
void fuse_enable_power(void);
void fuse_disable_power(void);
uint32_t fuse_get_sku_info(void);
uint32_t fuse_get_spare_bit(uint32_t index);
uint32_t fuse_get_reserved_odm(uint32_t index);
uint32_t fuse_get_bootrom_patch_version(void);
uint64_t fuse_get_device_id(void);
uint32_t fuse_get_dram_id(void);
uint32_t fuse_get_hardware_type_with_firmware_check(uint32_t target_firmware);
uint32_t fuse_get_hardware_type(void);
uint32_t fuse_get_retail_type(void);
void fuse_get_hardware_info(void *dst);
bool fuse_is_new_format(void);
uint32_t fuse_get_device_unique_key_generation(void);
uint32_t fuse_get_soc_type(void);
uint32_t fuse_get_regulator(void);
uint32_t fuse_hw_read(uint32_t addr);
void fuse_hw_write(uint32_t value, uint32_t addr);
void fuse_hw_sense(void);
#endif

0
fusee/fusee-primary/src/gpio.c → fusee/fusee-primary/fusee-primary-main/src/gpio.c
View file

0
fusee/fusee-primary/src/gpio.h → fusee/fusee-primary/fusee-primary-main/src/gpio.h
View file

271
fusee/fusee-primary/src/hwinit.c → fusee/fusee-primary/fusee-primary-main/src/hwinit.c
View file

@ -15,7 +15,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "hwinit.h"
#include "apb_misc.h"
#include "car.h"
@ -34,16 +34,20 @@
#include "timers.h"
#include "uart.h"
void config_oscillators()
{
/* Determine the current SoC for Mariko specific code. */
static bool is_soc_mariko() {
return (fuse_get_soc_type() == 1);
}
static void config_oscillators(void) {
volatile tegra_car_t *car = car_get_regs();
volatile tegra_pmc_t *pmc = pmc_get_regs();
car->spare_reg0 = ((car->spare_reg0 & 0xFFFFFFF3) | 4);
SYSCTR0_CNTFID0_0 = 19200000;
TIMERUS_USEC_CFG_0 = 0x45F;
car->osc_ctrl = 0x50000071;
pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFFFFF81) | 0xE);
pmc->osc_edpd_over = ((pmc->osc_edpd_over & 0xFFBFFFFF) | 0x400000);
@ -57,21 +61,23 @@ void config_oscillators()
car->clk_sys_rate = 2;
}
void config_gpios()
{
static void config_gpios(void) {
volatile tegra_pinmux_t *pinmux = pinmux_get_regs();
pinmux->uart2_tx = 0;
pinmux->uart3_tx = 0;
/* NOTE: This is also not done for calcio/copper. */
if (fuse_get_hardware_type() != 2) {
pinmux->uart2_tx = 0;
pinmux->uart3_tx = 0;
gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT);
gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT);
}
pinmux->pe6 = PINMUX_INPUT;
pinmux->ph6 = PINMUX_INPUT;
gpio_configure_mode(TEGRA_GPIO(G, 0), GPIO_MODE_GPIO);
gpio_configure_mode(TEGRA_GPIO(D, 1), GPIO_MODE_GPIO);
gpio_configure_mode(TEGRA_GPIO(E, 6), GPIO_MODE_GPIO);
gpio_configure_mode(TEGRA_GPIO(H, 6), GPIO_MODE_GPIO);
gpio_configure_direction(TEGRA_GPIO(G, 0), GPIO_DIRECTION_INPUT);
gpio_configure_direction(TEGRA_GPIO(D, 1), GPIO_DIRECTION_INPUT);
gpio_configure_direction(TEGRA_GPIO(E, 6), GPIO_DIRECTION_INPUT);
gpio_configure_direction(TEGRA_GPIO(H, 6), GPIO_DIRECTION_INPUT);
@ -79,26 +85,20 @@ void config_gpios()
i2c_config(I2C_5);
uart_config(UART_A);
/* Configure volume up/down as inputs. */
/* Configure volume up/down buttons as inputs. */
gpio_configure_mode(GPIO_BUTTON_VOL_UP, GPIO_MODE_GPIO);
gpio_configure_mode(GPIO_BUTTON_VOL_DOWN, GPIO_MODE_GPIO);
gpio_configure_direction(GPIO_BUTTON_VOL_UP, GPIO_DIRECTION_INPUT);
gpio_configure_direction(GPIO_BUTTON_VOL_DOWN, GPIO_DIRECTION_INPUT);
/* Configure home button as input. */
gpio_configure_mode(TEGRA_GPIO(Y, 1), GPIO_MODE_GPIO);
gpio_configure_direction(TEGRA_GPIO(Y, 1), GPIO_DIRECTION_INPUT);
}
void config_pmc_scratch()
{
volatile tegra_pmc_t *pmc = pmc_get_regs();
pmc->scratch20 &= 0xFFF3FFFF;
pmc->scratch190 &= 0xFFFFFFFE;
pmc->secure_scratch21 |= 0x10;
}
void mbist_workaround()
{
static void mbist_workaround(void) {
volatile tegra_car_t *car = car_get_regs();
car->clk_source_sor1 = ((car->clk_source_sor1 | 0x8000) & 0xFFFFBFFF);
car->plld_base |= 0x40800000u;
car->rst_dev_y_clr = 0x40;
@ -117,7 +117,7 @@ void mbist_workaround()
MAKE_I2S_REG(0x388) &= 0xFFFFFFFE;
MAKE_I2S_REG(0x4A0) |= 0x400;
MAKE_I2S_REG(0x488) &= 0xFFFFFFFE;
MAKE_DI_REG(DC_COM_DSC_TOP_CTL) |= 4;
MAKE_VIC_REG(0x8C) = 0xFFFFFFFF;
udelay(2);
@ -126,7 +126,7 @@ void mbist_workaround()
car->rst_dev_y_set = 0x40;
car->rst_dev_l_set = 0x18000000;
car->rst_dev_x_set = 0x40000;
/* Clock out enables. */
car->clk_out_enb_h = 0xC0;
car->clk_out_enb_l = 0x80000130;
@ -135,14 +135,14 @@ void mbist_workaround()
car->clk_out_enb_w = 0x402000FC;
car->clk_out_enb_x = 0x23000780;
car->clk_out_enb_y = 0x300;
/* LVL2 clock gate overrides. */
car->lvl2_clk_gate_ovra = 0;
car->lvl2_clk_gate_ovrb = 0;
car->lvl2_clk_gate_ovrc = 0;
car->lvl2_clk_gate_ovrd = 0;
car->lvl2_clk_gate_ovre = 0;
/* Configure clock sources. */
car->plld_base &= 0x1F7FFFFF;
car->clk_source_sor1 &= 0xFFFF3FFF;
@ -151,147 +151,164 @@ void mbist_workaround()
car->clk_source_nvenc = ((car->clk_source_nvenc & 0x1FFFFFFF) | 0x80000000);
}
void config_se_brom()
{
volatile tegra_fuse_chip_t *fuse_chip = fuse_chip_get_regs();
static void config_se_brom(void) {
volatile tegra_fuse_chip_common_t *fuse_chip = fuse_chip_common_get_regs();
volatile tegra_se_t *se = se_get_regs();
volatile tegra_pmc_t *pmc = pmc_get_regs();
/* Bootrom part we skipped. */
uint32_t sbk[4] = {fuse_chip->FUSE_PRIVATE_KEY[0], fuse_chip->FUSE_PRIVATE_KEY[1], fuse_chip->FUSE_PRIVATE_KEY[2], fuse_chip->FUSE_PRIVATE_KEY[3]};
set_aes_keyslot(0xE, sbk, 0x10);
/* Lock SBK from being read. */
se->SE_CRYPTO_KEYTABLE_ACCESS[0xE] = 0x7E;
/* This memset needs to happen here, else TZRAM will behave weirdly later on. */
memset((void *)0x7C010000, 0, 0x10000);
pmc->crypto_op = 0;
se->SE_INT_STATUS = 0x1F;
/* Lock SSK (although it's not set and unused anyways). */
se->SE_CRYPTO_KEYTABLE_ACCESS[0xF] = 0x7E;
/* Clear the boot reason to avoid problems later */
pmc->scratch200 = 0;
pmc->reset_status = 0;
pmc->rst_status = 0;
}
void nx_hwinit()
{
void nx_hwinit(bool enable_log) {
volatile tegra_pmc_t *pmc = pmc_get_regs();
volatile tegra_car_t *car = car_get_regs();
/* Bootrom stuff we skipped by going through RCM. */
config_se_brom();
AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
/* Apply the memory built-in self test workaround. */
mbist_workaround();
/* Reboot SE. */
bool is_mariko = is_soc_mariko();
if (!is_mariko) {
/* Bootrom stuff we skipped by going through RCM. */
config_se_brom();
AHB_AHB_SPARE_REG_0 &= 0xFFFFFF9F;
pmc->scratch49 = (((pmc->scratch49 >> 1) << 1) & 0xFFFFFFFD);
/* Apply the memory built-in self test workaround. */
mbist_workaround();
}
/* Enable SE clock. */
clkrst_reboot(CARDEVICE_SE);
if (is_mariko) {
/* Lock the SE clock. */
car->clk_source_se |= 0x100;
}
/* Initialize the fuse driver. */
fuse_init();
/* Initialize the memory controller. */
mc_enable();
if (!is_mariko) {
/* Initialize the memory controller. */
mc_enable();
}
/* Configure oscillators. */
config_oscillators();
/* Disable pinmux tristate input clamping. */
APB_MISC_PP_PINMUX_GLOBAL_0 = 0;
/* Configure GPIOs. */
/* NOTE: [3.0.0+] Part of the GPIO configuration is skipped if the unit is SDEV. */
/* NOTE: [6.0.0+] The GPIO configuration's order was changed a bit. */
config_gpios();
/* Uncomment for UART debugging. */
/*
clkrst_reboot(CARDEVICE_UARTC);
uart_init(UART_C, 115200);
*/
/* Reboot CL-DVFS. */
/* UART debugging. */
if (enable_log) {
clkrst_reboot(CARDEVICE_UARTA);
uart_init(UART_A, 115200);
}
/* Enable CL-DVFS clock. */
clkrst_reboot(CARDEVICE_CL_DVFS);
/* Reboot I2C1. */
/* Enable I2C1 clock. */
clkrst_reboot(CARDEVICE_I2C1);
/* Reboot I2C5. */
/* Enable I2C5 clock. */
clkrst_reboot(CARDEVICE_I2C5);
/* Reboot SE. */
/* NOTE: [4.0.0+] This was removed. */
/* clkrst_reboot(CARDEVICE_SE); */
/* Reboot TZRAM. */
/* Enable TZRAM clock. */
clkrst_reboot(CARDEVICE_TZRAM);
/* Initialize I2C1. */
/* NOTE: [6.0.0+] This was moved to after the PMIC is configured. */
i2c_init(I2C_1);
/* Initialize I2C5. */
i2c_init(I2C_5);
/* Configure the PMIC. */
uint8_t val = 0x40;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
val = 0x60;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
val = 0x38;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);
val = 0x3A;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1);
val = 0x38;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1);
val = 0xF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1);
val = 0xC7;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1);
val = 0x4F;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1);
val = 0x29;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
val = 0x1B;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
/* NOTE: [3.0.0+] This was added. */
val = 0x22;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
/*
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
val |= 0x40;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
*/
if (is_mariko) {
uint8_t val = 0x40;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
val = 0x78;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
} else {
uint8_t val = 0x40;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGBBC, &val, 1);
val = 0x60;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, &val, 1);
val = 0x38;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG0, &val, 1);
val = 0x3A;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG1, &val, 1);
val = 0x38;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_CFG2, &val, 1);
val = 0xF;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO4, &val, 1);
val = 0xC7;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_LDO8, &val, 1);
val = 0x4F;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD0, &val, 1);
val = 0x29;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD1, &val, 1);
val = 0x1B;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_SD3, &val, 1);
/* Configure SD0 voltage. */
val = 42; /* 42 = (1125000 - 600000) / 12500 -> 1.125V */
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
/* NOTE: [3.0.0+] This was added. */
val = 0x22;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_FPS_GPIO3, &val, 1);
/* Configure and lock PMC scratch registers. */
/* NOTE: [4.0.0+] This was removed. */
config_pmc_scratch();
/* TODO: In 3.x+, if the unit is SDEV, the MBLPD bit is set. */
/*
i2c_query(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
val |= 0x40;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_CNFGGLBL1, &val, 1);
*/
}
/* Configure SD0 voltage as 1.125v for erista, 1.050v for mariko. */
if (is_mariko) {
uint8_t val = 0x24;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
} else {
uint8_t val = 0x2A;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_SD0, &val, 1);
}
/* Enable LDO8 in HardwareType_Hoag only. */
if (fuse_get_hardware_type() == 2) {
uint8_t val = 0xE8;
i2c_send(I2C_5, MAX77620_PWR_I2C_ADDR, MAX77620_REG_LDO8_CFG, &val, 1);
}
/* Initialize I2C1. */
i2c_init(I2C_1);
/* Set super clock burst policy. */
car->sclk_brst_pol = ((car->sclk_brst_pol & 0xFFFF8888) | 0x3333);
/* Configure memory controller carveouts. */
/* NOTE: [4.0.0+] This is now done in the Secure Monitor. */
/* mc_config_carveout(); */
if (is_mariko) {
/* Mariko only PMC configuration for TZRAM. */
pmc->tzram_pwr_cntrl &= 0xFFFFFFFE;
pmc->tzram_non_sec_disable = 0x3;
pmc->tzram_sec_disable = 0x3;
}
/* Save SDRAM parameters to scratch. */
sdram_save_params(sdram_get_params(fuse_get_dram_id()));
/* Initialize SDRAM. */
sdram_init();
/* Save SDRAM LP0 parameters. */
sdram_lp0_save_params(sdram_get_params());
}

4
fusee/fusee-primary/src/hwinit.h → fusee/fusee-primary/fusee-primary-main/src/hwinit.h
View file

@ -19,9 +19,11 @@
#ifndef FUSEE_HWINIT_H_
#define FUSEE_HWINIT_H_
#include <stdbool.h>
#define I2S_BASE 0x702D1000
#define MAKE_I2S_REG(n) MAKE_REG32(I2S_BASE + n)
void nx_hwinit();
void nx_hwinit(bool enable_log);
#endif

0
fusee/fusee-primary/src/i2c.c → fusee/fusee-primary/fusee-primary-main/src/i2c.c
View file

14
fusee/fusee-primary/src/i2c.h → fusee/fusee-primary/fusee-primary-main/src/i2c.h
View file

@ -24,12 +24,14 @@
#define I2C1234_BASE 0x7000C000
#define I2C56_BASE 0x7000D000
#define MAX77621_CPU_I2C_ADDR 0x1B
#define MAX77621_GPU_I2C_ADDR 0x1C
#define MAX17050_I2C_ADDR 0x36
#define MAX77620_PWR_I2C_ADDR 0x3C
#define MAX77620_RTC_I2C_ADDR 0x68
#define BQ24193_I2C_ADDR 0x6B
#define MAX77621_CPU_I2C_ADDR 0x1B
#define MAX77621_GPU_I2C_ADDR 0x1C
#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31
#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33
#define MAX17050_I2C_ADDR 0x36
#define MAX77620_PWR_I2C_ADDR 0x3C
#define MAX77620_RTC_I2C_ADDR 0x68
#define BQ24193_I2C_ADDR 0x6B
typedef enum {
I2C_1 = 0,

0
fusee/fusee-primary/src/init.c → fusee/fusee-primary/fusee-primary-main/src/init.c
View file

15
fusee/fusee-primary/src/main.c → fusee/fusee-primary/fusee-primary-main/src/main.c
View file

@ -17,18 +17,19 @@
#include "utils.h"
#include "exception_handlers.h"
#include "panic.h"
#include "fuse.h"
#include "hwinit.h"
#include "di.h"
#include "timers.h"
#include "fs_utils.h"
#include "stage2.h"
#include "chainloader.h"
#include "sdmmc/sdmmc.h"
#include "lib/fatfs/ff.h"
#include "lib/log.h"
#include "lib/vsprintf.h"
#include "lib/ini.h"
#include "display/video_fb.h"
#include "../../../fusee/common/sdmmc/sdmmc.h"
#include "../../../fusee/common/fatfs/ff.h"
#include "../../../fusee/common/log.h"
#include "../../../fusee/common/vsprintf.h"
#include "../../../fusee/common/ini.h"
#include "../../../fusee/common/display/video_fb.h"
extern void (*__program_exit_callback)(int rc);
@ -118,7 +119,7 @@ static void cleanup_display(void) {
static void setup_env(void) {
/* Initialize hardware. */
nx_hwinit();
nx_hwinit(false);
/* Set up the exception handlers. */
setup_exception_handlers();

0
fusee/fusee-primary/src/max77620.h → fusee/fusee-primary/fusee-primary-main/src/max77620.h
View file

0
fusee/fusee-primary/src/max7762x.c → fusee/fusee-primary/fusee-primary-main/src/max7762x.c
View file

0
fusee/fusee-primary/src/max7762x.h → fusee/fusee-primary/fusee-primary-main/src/max7762x.h
View file

81
fusee/fusee-primary/fusee-primary-main/src/max77812.h Normal file
View file

@ -0,0 +1,81 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_MAX77812_H_
#define FUSEE_MAX77812_H_
#define MAX77812_REG_RESET 0x00
#define MAX77812_REG_INT_SRC 0x01
#define MAX77812_REG_INT_SRC_M 0x02
#define MAX77812_REG_TOPSYS_INT 0x03
#define MAX77812_REG_TOPSYS_INT_M 0x04
#define MAX77812_REG_TOPSYS_STAT 0x05
#define MAX77812_REG_EN_CTRL 0x06
#define MAX77812_REG_STUP_DLY1 0x07
#define MAX77812_REG_STUP_DLY2 0x08
#define MAX77812_REG_STUP_DLY3 0x09
#define MAX77812_REG_SHDN_DLY1 0x0A
#define MAX77812_REG_SHDN_DLY2 0x0B
#define MAX77812_REG_SHDN_DLY3 0x0C
#define MAX77812_REG_SHDN_DLY4 0x0D
#define MAX77812_REG_WDTRSTB_DEB 0x0E
#define MAX77812_REG_GPI_FUNC 0x0F
#define MAX77812_REG_GPI_DEB1 0x10
#define MAX77812_REG_GPI_DEB2 0x11
#define MAX77812_REG_GPI_PD_CTRL 0x12
#define MAX77812_REG_PROT_CFG 0x13
#define MAX77812_REG_I2C_CFG 0x15
#define MAX77812_REG_BUCK_INT 0x20
#define MAX77812_REG_BUCK_INT_M 0x21
#define MAX77812_REG_BUCK_STAT 0x22
#define MAX77812_REG_M1_VOUT 0x23
#define MAX77812_REG_M2_VOUT 0x24
#define MAX77812_REG_M3_VOUT 0x25
#define MAX77812_REG_M4_VOUT 0x26
#define MAX77812_REG_M1_VOUT_D 0x27
#define MAX77812_REG_M2_VOUT_D 0x28
#define MAX77812_REG_M3_VOUT_D 0x29
#define MAX77812_REG_M4_VOUT_D 0x2A
#define MAX77812_REG_M1_VOUT_S 0x2B
#define MAX77812_REG_M2_VOUT_S 0x2C
#define MAX77812_REG_M3_VOUT_S 0x2D
#define MAX77812_REG_M4_VOUT_S 0x2E
#define MAX77812_REG_M1_CGF 0x2F
#define MAX77812_REG_M2_CGF 0x30
#define MAX77812_REG_M3_CGF 0x31
#define MAX77812_REG_M4_CGF 0x32
#define MAX77812_REG_GLB_CFG1 0x33
#define MAX77812_REG_GLB_CFG2 0x34
#define MAX77812_REG_GLB_CFG3 0x35
#define MAX77812_REG_EN_CTRL_MASK(n) BIT(n)
#define MAX77812_START_SLEW_RATE_MASK 0x07
#define MAX77812_SHDN_SLEW_RATE_MASK 0x70
#define MAX77812_RAMPDOWN_SLEW_RATE_MASK 0x07
#define MAX77812_RAMPUP_SLEW_RATE_MASK 0x70
#define MAX77812_VOUT_MASK 0xFF
#define MAX77812_VOUT_N_VOLTAGE 0xFF
#define MAX77812_VOUT_VMIN 250000
#define MAX77812_VOUT_VMAX 1525000
#define MAX77812_VOUT_STEP 5000
#define MAX77812_REGULATOR_ID_M1 0
#define MAX77812_REGULATOR_ID_M2 1
#define MAX77812_REGULATOR_ID_M3 2
#define MAX77812_REGULATOR_ID_M4 3
#endif

0
fusee/fusee-primary/src/mc.c → fusee/fusee-primary/fusee-primary-main/src/mc.c
View file

1
fusee/fusee-primary/src/mc.h → fusee/fusee-primary/fusee-primary-main/src/mc.h
View file

@ -497,6 +497,7 @@
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08
#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0
#define MC_DA_CONFIG0 0x9dc
#define MC_UNTRANSLATED_REGION_CHECK 0x948
/* Memory Controller clients */
#define CLIENT_ACCESS_NUM_CLIENTS 32

4
fusee/fusee-primary/src/panic.c → fusee/fusee-primary/fusee-primary-main/src/panic.c
View file

@ -21,8 +21,8 @@
#include "fuse.h"
#include "utils.h"
#include "fs_utils.h"
#include "lib/log.h"
#include "display/video_fb.h"
#include "../../../fusee/common/log.h"
#include "../../../fusee/common/display/video_fb.h"
#define PROGRAM_ID_AMS_MITM 0x010041544D530000ull
#define PROGRAM_ID_BOOT 0x0100000000000005ull

0
fusee/fusee-primary/src/panic.h → fusee/fusee-primary/fusee-primary-main/src/panic.h
View file

0
fusee/fusee-primary/src/panic_color.h → fusee/fusee-primary/fusee-primary-main/src/panic_color.h
View file

0
fusee/fusee-primary/src/pinmux.h → fusee/fusee-primary/fusee-primary-main/src/pinmux.h
View file

713
fusee/fusee-primary/fusee-primary-main/src/pmc.h Normal file
View file

@ -0,0 +1,713 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FUSEE_PMC_H
#define FUSEE_PMC_H
#include <stdint.h>
#define PMC_BASE 0x7000E400
#define MAKE_PMC_REG(n) MAKE_REG32(PMC_BASE + n)
#define PMC_CONTROL_SDMMC1 (1 << 12)
#define PMC_CONTROL_SDMMC3 (1 << 13)
#define PMC_CONTROL_SDMMC4 (1 << 14)
#define APBDEV_PMC_CONTROL MAKE_PMC_REG(0x00)
#define APBDEV_PM_0 MAKE_PMC_REG(0x14)
#define APBDEV_PMC_DPD_ENABLE_0 MAKE_PMC_REG(0x24)
#define APBDEV_PMC_PWRGATE_TOGGLE_0 MAKE_PMC_REG(0x30)
#define APBDEV_PMC_PWRGATE_STATUS_0 MAKE_PMC_REG(0x38)
#define APBDEV_PMC_NO_IOPOWER_0 MAKE_PMC_REG(0x44)
#define APBDEV_PMC_SCRATCH0_0 MAKE_PMC_REG(0x50)
#define APBDEV_PMC_SCRATCH1_0 MAKE_PMC_REG(0x54)
#define APBDEV_PMC_SCRATCH20_0 MAKE_PMC_REG(0xA0)
#define APBDEV_PMC_PWR_DET_VAL_0 MAKE_PMC_REG(0xE4)
#define APBDEV_PMC_DDR_PWR_0 MAKE_PMC_REG(0xE8)
#define APBDEV_PMC_CRYPTO_OP_0 MAKE_PMC_REG(0xF4)
#define APBDEV_PMC_WAKE2_STATUS_0 MAKE_PMC_REG(0x168)
#define APBDEV_PMC_OSC_EDPD_OVER_0 MAKE_PMC_REG(0x1A4)
#define APBDEV_PMC_RST_STATUS_0 MAKE_PMC_REG(0x1B4)
#define APBDEV_PMC_IO_DPD_REQ_0 MAKE_PMC_REG(0x1B8)
#define APBDEV_PMC_IO_DPD2_REQ_0 MAKE_PMC_REG(0x1C0)
#define APBDEV_PMC_VDDP_SEL_0 MAKE_PMC_REG(0x1CC)
#define APBDEV_PMC_SCRATCH49_0 MAKE_PMC_REG(0x244)
#define APBDEV_PMC_TSC_MULT_0 MAKE_PMC_REG(0x2B4)
#define APBDEV_PMC_REG_SHORT_0 MAKE_PMC_REG(0x2CC)
#define APBDEV_PMC_WEAK_BIAS_0 MAKE_PMC_REG(0x2C8)
#define APBDEV_PMC_SECURE_SCRATCH21_0 MAKE_PMC_REG(0x334)
#define APBDEV_PMC_SECURE_SCRATCH32_0 MAKE_PMC_REG(0x360)
#define APBDEV_PMC_SECURE_SCRATCH49_0 MAKE_PMC_REG(0x3A4)
#define APBDEV_PMC_CNTRL2_0 MAKE_PMC_REG(0x440)
#define APBDEV_PMC_IO_DPD4_REQ_0 MAKE_PMC_REG(0x464)
#define APBDEV_PMC_UTMIP_PAD_CFG1_0 MAKE_PMC_REG(0x4C4)
#define APBDEV_PMC_UTMIP_PAD_CFG3_0 MAKE_PMC_REG(0x4CC)
#define APBDEV_PMC_DDR_CNTRL_0 MAKE_PMC_REG(0x4E4)
#define APBDEV_PMC_SCRATCH43_0 MAKE_PMC_REG(0x22C)
#define APBDEV_PMC_SCRATCH188_0 MAKE_PMC_REG(0x810)
#define APBDEV_PMC_SCRATCH190_0 MAKE_PMC_REG(0x818)
#define APBDEV_PMC_SCRATCH200_0 MAKE_PMC_REG(0x840)
#define APBDEV_PMC_SCRATCH45_0 MAKE_PMC_REG(0x234)
#define APBDEV_PMC_SCRATCH46_0 MAKE_PMC_REG(0x238)
#define APBDEV_PMC_SCRATCH33_0 MAKE_PMC_REG(0x120)
#define APBDEV_PMC_SCRATCH40_0 MAKE_PMC_REG(0x13C)
/* Power Management Controller (APBDEV_PMC_) regs */
typedef struct {
uint32_t cntrl; /* _CNTRL_0, 0x00 */
uint32_t sec_disable; /* _SEC_DISABLE_0, 0x04 */
uint32_t pmc_swrst; /* _PMC_SWRST_0, 0x08 */
uint32_t wake_mask; /* _WAKE_MASK_0, 0x0c */
uint32_t wake_lvl; /* _WAKE_LVL_0, 0x10 */
uint32_t wake_status; /* _WAKE_STATUS_0, 0x14 */
uint32_t sw_wake_status; /* _SW_WAKE_STATUS_0, 0x18 */
uint32_t dpd_pads_oride; /* _DPD_PADS_ORIDE_0, 0x1c */
uint32_t dpd_sample; /* _DPD_SAMPLE_0, 0x20 */
uint32_t dpd_enable; /* _DPD_ENABLE_0, 0x24 */
uint32_t pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, 0x28 */
uint32_t clamp_status; /* _CLAMP_STATUS_0, 0x2c */
uint32_t pwrgate_toggle; /* _PWRGATE_TOGGLE_0, 0x30 */
uint32_t remove_clamping; /* _REMOVE_CLAMPING_0, 0x34 */
uint32_t pwrgate_status; /* _PWRGATE_STATUS_0, 0x38 */
uint32_t pwrgood_timer; /* _PWRGOOD_TIMER_0, 0x3c */
uint32_t blink_timer; /* _BLINK_TIMER_0, 0x40 */
uint32_t no_iopower; /* _NO_IOPOWER_0, 0x44 */
uint32_t pwr_det; /* _PWR_DET_0, 0x48 */
uint32_t pwr_det_latch; /* _PWR_DET_LATCH_0, 0x4c */
uint32_t scratch0; /* _SCRATCH0_0, 0x50 */
uint32_t scratch1; /* _SCRATCH1_0, 0x54 */
uint32_t scratch2; /* _SCRATCH2_0, 0x58 */
uint32_t scratch3; /* _SCRATCH3_0, 0x5c */
uint32_t scratch4; /* _SCRATCH4_0, 0x60 */
uint32_t scratch5; /* _SCRATCH5_0, 0x64 */
uint32_t scratch6; /* _SCRATCH6_0, 0x68 */
uint32_t scratch7; /* _SCRATCH7_0, 0x6c */
uint32_t scratch8; /* _SCRATCH8_0, 0x70 */
uint32_t scratch9; /* _SCRATCH9_0, 0x74 */
uint32_t scratch10; /* _SCRATCH10_0, 0x78 */
uint32_t scratch11; /* _SCRATCH11_0, 0x7c */
uint32_t scratch12; /* _SCRATCH12_0, 0x80 */
uint32_t scratch13; /* _SCRATCH13_0, 0x84 */
uint32_t scratch14; /* _SCRATCH14_0, 0x88 */
uint32_t scratch15; /* _SCRATCH15_0, 0x8c */
uint32_t scratch16; /* _SCRATCH16_0, 0x90 */
uint32_t scratch17; /* _SCRATCH17_0, 0x94 */
uint32_t scratch18; /* _SCRATCH18_0, 0x98 */
uint32_t scratch19; /* _SCRATCH19_0, 0x9c */
uint32_t scratch20; /* _SCRATCH20_0, 0xa0 */
uint32_t scratch21; /* _SCRATCH21_0, 0xa4 */
uint32_t scratch22; /* _SCRATCH22_0, 0xa8 */
uint32_t scratch23; /* _SCRATCH23_0, 0xac */
uint32_t secure_scratch0; /* _SECURE_SCRATCH0_0, 0xb0 */
uint32_t secure_scratch1; /* _SECURE_SCRATCH1_0, 0xb4 */
uint32_t secure_scratch2; /* _SECURE_SCRATCH2_0, 0xb8 */
uint32_t secure_scratch3; /* _SECURE_SCRATCH3_0, 0xbc */
uint32_t secure_scratch4; /* _SECURE_SCRATCH4_0, 0xc0 */
uint32_t secure_scratch5; /* _SECURE_SCRATCH5_0, 0xc4 */
uint32_t cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, 0xc8 */
uint32_t cpupwroff_timer; /* _CPUPWROFF_TIMER_0, 0xcc */
uint32_t pg_mask; /* _PG_MASK_0, 0xd0 */
uint32_t pg_mask_1; /* _PG_MASK_1_0, 0xd4 */
uint32_t auto_wake_lvl; /* _AUTO_WAKE_LVL_0, 0xd8 */
uint32_t auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, 0xdc */
uint32_t wake_delay; /* _WAKE_DELAY_0, 0xe0 */
uint32_t pwr_det_val; /* _PWR_DET_VAL_0, 0xe4 */
uint32_t ddr_pwr; /* _DDR_PWR_0, 0xe8 */
uint32_t usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, 0xec */
uint32_t usb_ao; /* _USB_AO_0, 0xf0 */
uint32_t crypto_op; /* _CRYPTO_OP_0, 0xf4 */
uint32_t pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, 0xf8 */
uint32_t scratch24; /* _SCRATCH24_0, 0xfc */
uint32_t scratch25; /* _SCRATCH25_0, 0x100 */
uint32_t scratch26; /* _SCRATCH26_0, 0x104 */
uint32_t scratch27; /* _SCRATCH27_0, 0x108 */
uint32_t scratch28; /* _SCRATCH28_0, 0x10c */
uint32_t scratch29; /* _SCRATCH29_0, 0x110 */
uint32_t scratch30; /* _SCRATCH30_0, 0x114 */
uint32_t scratch31; /* _SCRATCH31_0, 0x118 */
uint32_t scratch32; /* _SCRATCH32_0, 0x11c */
uint32_t scratch33; /* _SCRATCH33_0, 0x120 */
uint32_t scratch34; /* _SCRATCH34_0, 0x124 */
uint32_t scratch35; /* _SCRATCH35_0, 0x128 */
uint32_t scratch36; /* _SCRATCH36_0, 0x12c */
uint32_t scratch37; /* _SCRATCH37_0, 0x130 */
uint32_t scratch38; /* _SCRATCH38_0, 0x134 */
uint32_t scratch39; /* _SCRATCH39_0, 0x138 */
uint32_t scratch40; /* _SCRATCH40_0, 0x13c */
uint32_t scratch41; /* _SCRATCH41_0, 0x140 */
uint32_t scratch42; /* _SCRATCH42_0, 0x144 */
uint32_t bondout_mirror0; /* _BONDOUT_MIRROR0_0, 0x148 */
uint32_t bondout_mirror1; /* _BONDOUT_MIRROR1_0, 0x14c */
uint32_t bondout_mirror2; /* _BONDOUT_MIRROR2_0, 0x150 */
uint32_t sys_33v_en; /* _SYS_33V_EN_0, 0x154 */
uint32_t bondout_mirror_access; /* _BONDOUT_MIRROR_ACCESS_0, 0x158 */
uint32_t gate; /* _GATE_0, 0x15c */
uint32_t wake2_mask; /* _WAKE2_MASK_0, 0x160 */
uint32_t wake2_lvl; /* _WAKE2_LVL_0, 0x164 */
uint32_t wake2_status; /* _WAKE2_STATUS_0, 0x168 */
uint32_t sw_wake2_status; /* _SW_WAKE2_STATUS_0, 0x16c */
uint32_t auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, 0x170 */
uint32_t pg_mask_2; /* _PG_MASK_2_0, 0x174 */
uint32_t pg_mask_ce1; /* _PG_MASK_CE1_0, 0x178 */
uint32_t pg_mask_ce2; /* _PG_MASK_CE2_0, 0x17c */
uint32_t pg_mask_ce3; /* _PG_MASK_CE3_0, 0x180 */
uint32_t pwrgate_timer_ce_0; /* _PWRGATE_TIMER_CE_0_0, 0x184 */
uint32_t pwrgate_timer_ce_1; /* _PWRGATE_TIMER_CE_1_0, 0x188 */
uint32_t pwrgate_timer_ce_2; /* _PWRGATE_TIMER_CE_2_0, 0x18c */
uint32_t pwrgate_timer_ce_3; /* _PWRGATE_TIMER_CE_3_0, 0x190 */
uint32_t pwrgate_timer_ce_4; /* _PWRGATE_TIMER_CE_4_0, 0x194 */
uint32_t pwrgate_timer_ce_5; /* _PWRGATE_TIMER_CE_5_0, 0x198 */
uint32_t pwrgate_timer_ce_6; /* _PWRGATE_TIMER_CE_6_0, 0x19c */
uint32_t pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, 0x1a0 */
uint32_t osc_edpd_over; /* _OSC_EDPD_OVER_0, 0x1a4 */
uint32_t clk_out_cntrl; /* _CLK_OUT_CNTRL_0, 0x1a8 */
uint32_t sata_pwrgt; /* _SATA_PWRGT_0, 0x1ac */
uint32_t sensor_ctrl; /* _SENSOR_CTRL_0, 0x1b0 */
uint32_t rst_status; /* _RST_STATUS_0, 0x1b4 */
uint32_t io_dpd_req; /* _IO_DPD_REQ_0, 0x1b8 */
uint32_t io_dpd_status; /* _IO_DPD_STATUS_0, 0x1bc */
uint32_t io_dpd2_req; /* _IO_DPD2_REQ_0, 0x1c0 */
uint32_t io_dpd2_status; /* _IO_DPD2_STATUS_0, 0x1c4 */
uint32_t sel_dpd_tim; /* _SEL_DPD_TIM_0, 0x1c8 */
uint32_t vddp_sel; /* _VDDP_SEL_0, 0x1cc */
uint32_t ddr_cfg; /* _DDR_CFG_0, 0x1d0 */
uint32_t _0x1d4[2];
uint32_t pllm_wb0_override_freq; /* _PLLM_WB0_OVERRIDE_FREQ_0, 0x1dc */
uint32_t _0x1e0;
uint32_t pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, 0x1e4 */
uint32_t dsi_sel_dpd; /* _DSI_SEL_DPD_0, 0x1e8 */
uint32_t utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, 0x1ec */
uint32_t utmip_uhsic_saved_state; /* _UTMIP_UHSIC_SAVED_STATE_0, 0x1f0 */
uint32_t _0x1f4;
uint32_t utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, 0x1f8 */
uint32_t utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, 0x1fc */
uint32_t utmip_uhsic_sleepwalk_cfg; /* _UTMIP_UHSIC_SLEEPWALK_CFG_0, 0x200 */
uint32_t utmip_sleepwalk_p0; /* _UTMIP_SLEEPWALK_P0_0, 0x204 */
uint32_t utmip_sleepwalk_p1; /* _UTMIP_SLEEPWALK_P1_0, 0x208 */
uint32_t utmip_sleepwalk_p2; /* _UTMIP_SLEEPWALK_P2_0, 0x20c */
uint32_t uhsic_sleepwalk_p0; /* _UHSIC_SLEEPWALK_P0_0, 0x210 */
uint32_t utmip_uhsic_status; /* _UTMIP_UHSIC_STATUS_0, 0x214 */
uint32_t utmip_uhsic_fake; /* _UTMIP_UHSIC_FAKE_0, 0x218 */
uint32_t bondout_mirror3; /* _BONDOUT_MIRROR3_0, 0x21c */
uint32_t bondout_mirror4; /* _BONDOUT_MIRROR4_0, 0x220 */
uint32_t secure_scratch6; /* _SECURE_SCRATCH6_0, 0x224 */
uint32_t secure_scratch7; /* _SECURE_SCRATCH7_0, 0x228 */
uint32_t scratch43; /* _SCRATCH43_0, 0x22c */
uint32_t scratch44; /* _SCRATCH44_0, 0x230 */
uint32_t scratch45; /* _SCRATCH45_0, 0x234 */
uint32_t scratch46; /* _SCRATCH46_0, 0x238 */
uint32_t scratch47; /* _SCRATCH47_0, 0x23c */
uint32_t scratch48; /* _SCRATCH48_0, 0x240 */
uint32_t scratch49; /* _SCRATCH49_0, 0x244 */
uint32_t scratch50; /* _SCRATCH50_0, 0x248 */
uint32_t scratch51; /* _SCRATCH51_0, 0x24c */
uint32_t scratch52; /* _SCRATCH52_0, 0x250 */
uint32_t scratch53; /* _SCRATCH53_0, 0x254 */
uint32_t scratch54; /* _SCRATCH54_0, 0x258 */
uint32_t scratch55; /* _SCRATCH55_0, 0x25c */
uint32_t scratch0_eco; /* _SCRATCH0_ECO_0, 0x260 */
uint32_t por_dpd_ctrl; /* _POR_DPD_CTRL_0, 0x264 */
uint32_t scratch2_eco; /* _SCRATCH2_ECO_0, 0x268 */
uint32_t utmip_uhsic_line_wakeup; /* _UTMIP_UHSIC_LINE_WAKEUP_0, 0x26c */
uint32_t utmip_bias_master_cntrl; /* _UTMIP_BIAS_MASTER_CNTRL_0, 0x270 */
uint32_t utmip_master_config; /* _UTMIP_MASTER_CONFIG_0, 0x274 */
uint32_t td_pwrgate_inter_part_timer; /* _TD_PWRGATE_INTER_PART_TIMER_0, 0x278 */
uint32_t utmip_uhsic2_triggers; /* _UTMIP_UHSIC2_TRIGGERS_0, 0x27c */
uint32_t utmip_uhsic2_saved_state; /* _UTMIP_UHSIC2_SAVED_STATE_0, 0x280 */
uint32_t utmip_uhsic2_sleep_cfg; /* _UTMIP_UHSIC2_SLEEP_CFG_0, 0x284 */
uint32_t utmip_uhsic2_sleepwalk_cfg; /* _UTMIP_UHSIC2_SLEEPWALK_CFG_0, 0x288 */
uint32_t uhsic2_sleepwalk_p1; /* _UHSIC2_SLEEPWALK_P1_0, 0x28c */
uint32_t utmip_uhsic2_status; /* _UTMIP_UHSIC2_STATUS_0, 0x290 */
uint32_t utmip_uhsic2_fake; /* _UTMIP_UHSIC2_FAKE_0, 0x294 */
uint32_t utmip_uhsic2_line_wakeup; /* _UTMIP_UHSIC2_LINE_WAKEUP_0, 0x298 */
uint32_t utmip_master2_config; /* _UTMIP_MASTER2_CONFIG_0, 0x29c */
uint32_t utmip_uhsic_rpd_cfg; /* _UTMIP_UHSIC_RPD_CFG_0, 0x2a0 */
uint32_t pg_mask_ce0; /* _PG_MASK_CE0_0, 0x2a4 */
uint32_t pg_mask_3; /* _PG_MASK_3_0, 0x2a8 */
uint32_t pg_mask_4; /* _PG_MASK_4_0, 0x2ac */
uint32_t pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2_0, 0x2b0 */
uint32_t tsc_mult; /* _TSC_MULT_0, 0x2b4 */
uint32_t cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, 0x2b8 */
uint32_t glb_amap_cfg; /* _GLB_AMAP_CFG_0, 0x2bc */
uint32_t sticky_bits; /* _STICKY_BITS_0, 0x2c0 */
uint32_t sec_disable2; /* _SEC_DISABLE2_0, 0x2c4 */
uint32_t weak_bias; /* _WEAK_BIAS_0, 0x2c8 */
uint32_t reg_short; /* _REG_SHORT_0, 0x2cc */
uint32_t pg_mask_andor; /* _PG_MASK_ANDOR_0, 0x2d0 */
uint32_t gpu_rg_cntrl; /* _GPU_RG_CNTRL_0, 0x2d4 */
uint32_t sec_disable3; /* _SEC_DISABLE3_0, 0x2d8 */
uint32_t pg_mask_5; /* _PG_MASK_5_0, 0x2dc */
uint32_t pg_mask_6; /* _PG_MASK_6_0, 0x2e0 */
uint32_t _0x2e4[7];
uint32_t secure_scratch8; /* _SECURE_SCRATCH8_0, 0x300 */
uint32_t secure_scratch9; /* _SECURE_SCRATCH9_0, 0x304 */
uint32_t secure_scratch10; /* _SECURE_SCRATCH10_0, 0x308 */
uint32_t secure_scratch11; /* _SECURE_SCRATCH11_0, 0x30c */
uint32_t secure_scratch12; /* _SECURE_SCRATCH12_0, 0x310 */
uint32_t secure_scratch13; /* _SECURE_SCRATCH13_0, 0x314 */
uint32_t secure_scratch14; /* _SECURE_SCRATCH14_0, 0x318 */
uint32_t secure_scratch15; /* _SECURE_SCRATCH15_0, 0x31c */
uint32_t secure_scratch16; /* _SECURE_SCRATCH16_0, 0x320 */
uint32_t secure_scratch17; /* _SECURE_SCRATCH17_0, 0x324 */
uint32_t secure_scratch18; /* _SECURE_SCRATCH18_0, 0x328 */
uint32_t secure_scratch19; /* _SECURE_SCRATCH19_0, 0x32c */
uint32_t secure_scratch20; /* _SECURE_SCRATCH20_0, 0x330 */
uint32_t secure_scratch21; /* _SECURE_SCRATCH21_0, 0x334 */
uint32_t secure_scratch22; /* _SECURE_SCRATCH22_0, 0x338 */
uint32_t secure_scratch23; /* _SECURE_SCRATCH23_0, 0x33c */
uint32_t secure_scratch24; /* _SECURE_SCRATCH24_0, 0x340 */
uint32_t secure_scratch25; /* _SECURE_SCRATCH25_0, 0x344 */
uint32_t secure_scratch26; /* _SECURE_SCRATCH26_0, 0x348 */
uint32_t secure_scratch27; /* _SECURE_SCRATCH27_0, 0x34c */
uint32_t secure_scratch28; /* _SECURE_SCRATCH28_0, 0x350 */
uint32_t secure_scratch29; /* _SECURE_SCRATCH29_0, 0x354 */
uint32_t secure_scratch30; /* _SECURE_SCRATCH30_0, 0x358 */
uint32_t secure_scratch31; /* _SECURE_SCRATCH31_0, 0x35c */
uint32_t secure_scratch32; /* _SECURE_SCRATCH32_0, 0x360 */
uint32_t secure_scratch33; /* _SECURE_SCRATCH33_0, 0x364 */
uint32_t secure_scratch34; /* _SECURE_SCRATCH34_0, 0x368 */
uint32_t secure_scratch35; /* _SECURE_SCRATCH35_0, 0x36c */
uint32_t secure_scratch36; /* _SECURE_SCRATCH36_0, 0x370 */
uint32_t secure_scratch37; /* _SECURE_SCRATCH37_0, 0x374 */
uint32_t secure_scratch38; /* _SECURE_SCRATCH38_0, 0x378 */
uint32_t secure_scratch39; /* _SECURE_SCRATCH39_0, 0x37c */
uint32_t secure_scratch40; /* _SECURE_SCRATCH40_0, 0x380 */
uint32_t secure_scratch41; /* _SECURE_SCRATCH41_0, 0x384 */
uint32_t secure_scratch42; /* _SECURE_SCRATCH42_0, 0x388 */
uint32_t secure_scratch43; /* _SECURE_SCRATCH43_0, 0x38c */
uint32_t secure_scratch44; /* _SECURE_SCRATCH44_0, 0x390 */
uint32_t secure_scratch45; /* _SECURE_SCRATCH45_0, 0x394 */
uint32_t secure_scratch46; /* _SECURE_SCRATCH46_0, 0x398 */
uint32_t secure_scratch47; /* _SECURE_SCRATCH47_0, 0x39c */
uint32_t secure_scratch48; /* _SECURE_SCRATCH48_0, 0x3a0 */
uint32_t secure_scratch49; /* _SECURE_SCRATCH49_0, 0x3a4 */
uint32_t secure_scratch50; /* _SECURE_SCRATCH50_0, 0x3a8 */
uint32_t secure_scratch51; /* _SECURE_SCRATCH51_0, 0x3ac */
uint32_t secure_scratch52; /* _SECURE_SCRATCH52_0, 0x3b0 */
uint32_t secure_scratch53; /* _SECURE_SCRATCH53_0, 0x3b4 */
uint32_t secure_scratch54; /* _SECURE_SCRATCH54_0, 0x3b8 */
uint32_t secure_scratch55; /* _SECURE_SCRATCH55_0, 0x3bc */
uint32_t secure_scratch56; /* _SECURE_SCRATCH56_0, 0x3c0 */
uint32_t secure_scratch57; /* _SECURE_SCRATCH57_0, 0x3c4 */
uint32_t secure_scratch58; /* _SECURE_SCRATCH58_0, 0x3c8 */
uint32_t secure_scratch59; /* _SECURE_SCRATCH59_0, 0x3cc */
uint32_t secure_scratch60; /* _SECURE_SCRATCH60_0, 0x3d0 */
uint32_t secure_scratch61; /* _SECURE_SCRATCH61_0, 0x3d4 */
uint32_t secure_scratch62; /* _SECURE_SCRATCH62_0, 0x3d8 */
uint32_t secure_scratch63; /* _SECURE_SCRATCH63_0, 0x3dc */
uint32_t secure_scratch64; /* _SECURE_SCRATCH64_0, 0x3e0 */
uint32_t secure_scratch65; /* _SECURE_SCRATCH65_0, 0x3e4 */
uint32_t secure_scratch66; /* _SECURE_SCRATCH66_0, 0x3e8 */
uint32_t secure_scratch67; /* _SECURE_SCRATCH67_0, 0x3ec */
uint32_t secure_scratch68; /* _SECURE_SCRATCH68_0, 0x3f0 */
uint32_t secure_scratch69; /* _SECURE_SCRATCH69_0, 0x3f4 */
uint32_t secure_scratch70; /* _SECURE_SCRATCH70_0, 0x3f8 */
uint32_t secure_scratch71; /* _SECURE_SCRATCH71_0, 0x3fc */
uint32_t secure_scratch72; /* _SECURE_SCRATCH72_0, 0x400 */
uint32_t secure_scratch73; /* _SECURE_SCRATCH73_0, 0x404 */
uint32_t secure_scratch74; /* _SECURE_SCRATCH74_0, 0x408 */
uint32_t secure_scratch75; /* _SECURE_SCRATCH75_0, 0x40c */
uint32_t secure_scratch76; /* _SECURE_SCRATCH76_0, 0x410 */
uint32_t secure_scratch77; /* _SECURE_SCRATCH77_0, 0x414 */
uint32_t secure_scratch78; /* _SECURE_SCRATCH78_0, 0x418 */
uint32_t secure_scratch79; /* _SECURE_SCRATCH79_0, 0x41c */
uint32_t _0x420[8];
uint32_t cntrl2; /* _CNTRL2_0, 0x440 */
uint32_t io_dpd_off_mask; /* _IO_DPD_OFF_MASK_0, 0x444 */
uint32_t io_dpd2_off_mask; /* _IO_DPD2_OFF_MASK_0, 0x448 */
uint32_t event_counter; /* _EVENT_COUNTER_0, 0x44c */
uint32_t fuse_control; /* _FUSE_CONTROL_0, 0x450 */
uint32_t scratch1_eco; /* _SCRATCH1_ECO_0, 0x454 */
uint32_t _0x458;
uint32_t io_dpd3_req; /* _IO_DPD3_REQ_0, 0x45c */
uint32_t io_dpd3_status; /* _IO_DPD3_STATUS_0, 0x460 */
uint32_t io_dpd4_req; /* _IO_DPD4_REQ_0, 0x464 */
uint32_t io_dpd4_status; /* _IO_DPD4_STATUS_0, 0x468 */
uint32_t _0x46c[2];
uint32_t direct_thermtrip_cfg; /* _DIRECT_THERMTRIP_CFG_0, 0x474 */
uint32_t tsosc_delay; /* _TSOSC_DELAY_0, 0x478 */
uint32_t set_sw_clamp; /* _SET_SW_CLAMP_0, 0x47c */
uint32_t debug_authentication; /* _DEBUG_AUTHENTICATION_0, 0x480 */
uint32_t aotag_cfg; /* _AOTAG_CFG_0, 0x484 */
uint32_t aotag_thresh1_cfg; /* _AOTAG_THRESH1_CFG_0, 0x488 */
uint32_t aotag_thresh2_cfg; /* _AOTAG_THRESH2_CFG_0, 0x48c */
uint32_t aotag_thresh3_cfg; /* _AOTAG_THRESH3_CFG_0, 0x490 */
uint32_t aotag_status; /* _AOTAG_STATUS_0, 0x494 */
uint32_t aotag_security; /* _AOTAG_SECURITY_0, 0x498 */
uint32_t tsensor_config0; /* _TSENSOR_CONFIG0_0, 0x49c */
uint32_t tsensor_config1; /* _TSENSOR_CONFIG1_0, 0x4a0 */
uint32_t tsensor_config2; /* _TSENSOR_CONFIG2_0, 0x4a4 */
uint32_t tsensor_status0; /* _TSENSOR_STATUS0_0, 0x4a8 */
uint32_t tsensor_status1; /* _TSENSOR_STATUS1_0, 0x4ac */
uint32_t tsensor_status2; /* _TSENSOR_STATUS2_0, 0x4b0 */
uint32_t tsensor_pdiv; /* _TSENSOR_PDIV_0, 0x4b4 */
uint32_t aotag_intr_en; /* _AOTAG_INTR_EN_0, 0x4b8 */
uint32_t aotag_intr_dis; /* _AOTAG_INTR_DIS_0, 0x4bc */
uint32_t utmip_pad_cfg0; /* _UTMIP_PAD_CFG0_0, 0x4c0 */
uint32_t utmip_pad_cfg1; /* _UTMIP_PAD_CFG1_0, 0x4c4 */
uint32_t utmip_pad_cfg2; /* _UTMIP_PAD_CFG2_0, 0x4c8 */
uint32_t utmip_pad_cfg3; /* _UTMIP_PAD_CFG3_0, 0x4cc */
uint32_t utmip_uhsic_sleep_cfg1; /* _UTMIP_UHSIC_SLEEP_CFG1_0, 0x4d0 */
uint32_t cc4_hvc_control; /* _CC4_HVC_CONTROL_0, 0x4d4 */
uint32_t wake_debounce_en; /* _WAKE_DEBOUNCE_EN_0, 0x4d8 */
uint32_t ramdump_ctl_status; /* _RAMDUMP_CTL_STATUS_0, 0x4dc */
uint32_t utmip_sleepwalk_p3; /* _UTMIP_SLEEPWALK_P3_0, 0x4e0 */
uint32_t ddr_cntrl; /* _DDR_CNTRL_0, 0x4e4 */
uint32_t _0x4e8[50];
uint32_t sec_disable4; /* _SEC_DISABLE4_0, 0x5b0 */
uint32_t sec_disable5; /* _SEC_DISABLE5_0, 0x5b4 */
uint32_t sec_disable6; /* _SEC_DISABLE6_0, 0x5b8 */
uint32_t sec_disable7; /* _SEC_DISABLE7_0, 0x5bc */
uint32_t sec_disable8; /* _SEC_DISABLE8_0, 0x5c0 */
uint32_t sec_disable9; /* _SEC_DISABLE9_0, 0x5c4 */
uint32_t sec_disable10; /* _SEC_DISABLE10_0, 0x5c8 */
uint32_t _0x5cc[13];
uint32_t scratch56; /* _SCRATCH56_0, 0x600 */
uint32_t scratch57; /* _SCRATCH57_0, 0x604 */
uint32_t scratch58; /* _SCRATCH58_0, 0x608 */
uint32_t scratch59; /* _SCRATCH59_0, 0x60c */
uint32_t scratch60; /* _SCRATCH60_0, 0x610 */
uint32_t scratch61; /* _SCRATCH61_0, 0x614 */
uint32_t scratch62; /* _SCRATCH62_0, 0x618 */
uint32_t scratch63; /* _SCRATCH63_0, 0x61c */
uint32_t scratch64; /* _SCRATCH64_0, 0x620 */
uint32_t scratch65; /* _SCRATCH65_0, 0x624 */
uint32_t scratch66; /* _SCRATCH66_0, 0x628 */
uint32_t scratch67; /* _SCRATCH67_0, 0x62c */
uint32_t scratch68; /* _SCRATCH68_0, 0x630 */
uint32_t scratch69; /* _SCRATCH69_0, 0x634 */
uint32_t scratch70; /* _SCRATCH70_0, 0x638 */
uint32_t scratch71; /* _SCRATCH71_0, 0x63c */
uint32_t scratch72; /* _SCRATCH72_0, 0x640 */
uint32_t scratch73; /* _SCRATCH73_0, 0x644 */
uint32_t scratch74; /* _SCRATCH74_0, 0x648 */
uint32_t scratch75; /* _SCRATCH75_0, 0x64c */
uint32_t scratch76; /* _SCRATCH76_0, 0x650 */
uint32_t scratch77; /* _SCRATCH77_0, 0x654 */
uint32_t scratch78; /* _SCRATCH78_0, 0x658 */
uint32_t scratch79; /* _SCRATCH79_0, 0x65c */
uint32_t scratch80; /* _SCRATCH80_0, 0x660 */
uint32_t scratch81; /* _SCRATCH81_0, 0x664 */
uint32_t scratch82; /* _SCRATCH82_0, 0x668 */
uint32_t scratch83; /* _SCRATCH83_0, 0x66c */
uint32_t scratch84; /* _SCRATCH84_0, 0x670 */
uint32_t scratch85; /* _SCRATCH85_0, 0x674 */
uint32_t scratch86; /* _SCRATCH86_0, 0x678 */
uint32_t scratch87; /* _SCRATCH87_0, 0x67c */
uint32_t scratch88; /* _SCRATCH88_0, 0x680 */
uint32_t scratch89; /* _SCRATCH89_0, 0x684 */
uint32_t scratch90; /* _SCRATCH90_0, 0x688 */
uint32_t scratch91; /* _SCRATCH91_0, 0x68c */
uint32_t scratch92; /* _SCRATCH92_0, 0x690 */
uint32_t scratch93; /* _SCRATCH93_0, 0x694 */
uint32_t scratch94; /* _SCRATCH94_0, 0x698 */
uint32_t scratch95; /* _SCRATCH95_0, 0x69c */
uint32_t scratch96; /* _SCRATCH96_0, 0x6a0 */
uint32_t scratch97; /* _SCRATCH97_0, 0x6a4 */
uint32_t scratch98; /* _SCRATCH98_0, 0x6a8 */
uint32_t scratch99; /* _SCRATCH99_0, 0x6ac */
uint32_t scratch100; /* _SCRATCH100_0, 0x6b0 */
uint32_t scratch101; /* _SCRATCH101_0, 0x6b4 */
uint32_t scratch102; /* _SCRATCH102_0, 0x6b8 */
uint32_t scratch103; /* _SCRATCH103_0, 0x6bc */
uint32_t scratch104; /* _SCRATCH104_0, 0x6c0 */
uint32_t scratch105; /* _SCRATCH105_0, 0x6c4 */
uint32_t scratch106; /* _SCRATCH106_0, 0x6c8 */
uint32_t scratch107; /* _SCRATCH107_0, 0x6cc */
uint32_t scratch108; /* _SCRATCH108_0, 0x6d0 */
uint32_t scratch109; /* _SCRATCH109_0, 0x6d4 */
uint32_t scratch110; /* _SCRATCH110_0, 0x6d8 */
uint32_t scratch111; /* _SCRATCH111_0, 0x6dc */
uint32_t scratch112; /* _SCRATCH112_0, 0x6e0 */
uint32_t scratch113; /* _SCRATCH113_0, 0x6e4 */
uint32_t scratch114; /* _SCRATCH114_0, 0x6e8 */
uint32_t scratch115; /* _SCRATCH115_0, 0x6ec */
uint32_t scratch116; /* _SCRATCH116_0, 0x6f0 */
uint32_t scratch117; /* _SCRATCH117_0, 0x6f4 */
uint32_t scratch118; /* _SCRATCH118_0, 0x6f8 */
uint32_t scratch119; /* _SCRATCH119_0, 0x6fc */
uint32_t scratch120; /* _SCRATCH120_0, 0x700 */
uint32_t scratch121; /* _SCRATCH121_0, 0x704 */
uint32_t scratch122; /* _SCRATCH122_0, 0x708 */
uint32_t scratch123; /* _SCRATCH123_0, 0x70c */
uint32_t scratch124; /* _SCRATCH124_0, 0x710 */
uint32_t scratch125; /* _SCRATCH125_0, 0x714 */
uint32_t scratch126; /* _SCRATCH126_0, 0x718 */
uint32_t scratch127; /* _SCRATCH127_0, 0x71c */
uint32_t scratch128; /* _SCRATCH128_0, 0x720 */
uint32_t scratch129; /* _SCRATCH129_0, 0x724 */
uint32_t scratch130; /* _SCRATCH130_0, 0x728 */
uint32_t scratch131; /* _SCRATCH131_0, 0x72c */
uint32_t scratch132; /* _SCRATCH132_0, 0x730 */
uint32_t scratch133; /* _SCRATCH133_0, 0x734 */
uint32_t scratch134; /* _SCRATCH134_0, 0x738 */
uint32_t scratch135; /* _SCRATCH135_0, 0x73c */
uint32_t scratch136; /* _SCRATCH136_0, 0x740 */
uint32_t scratch137; /* _SCRATCH137_0, 0x744 */
uint32_t scratch138; /* _SCRATCH138_0, 0x748 */
uint32_t scratch139; /* _SCRATCH139_0, 0x74c */
uint32_t scratch140; /* _SCRATCH140_0, 0x750 */
uint32_t scratch141; /* _SCRATCH141_0, 0x754 */
uint32_t scratch142; /* _SCRATCH142_0, 0x758 */
uint32_t scratch143; /* _SCRATCH143_0, 0x75c */
uint32_t scratch144; /* _SCRATCH144_0, 0x760 */
uint32_t scratch145; /* _SCRATCH145_0, 0x764 */
uint32_t scratch146; /* _SCRATCH146_0, 0x768 */
uint32_t scratch147; /* _SCRATCH147_0, 0x76c */
uint32_t scratch148; /* _SCRATCH148_0, 0x770 */
uint32_t scratch149; /* _SCRATCH149_0, 0x774 */
uint32_t scratch150; /* _SCRATCH150_0, 0x778 */
uint32_t scratch151; /* _SCRATCH151_0, 0x77c */
uint32_t scratch152; /* _SCRATCH152_0, 0x780 */
uint32_t scratch153; /* _SCRATCH153_0, 0x784 */
uint32_t scratch154; /* _SCRATCH154_0, 0x788 */
uint32_t scratch155; /* _SCRATCH155_0, 0x78c */
uint32_t scratch156; /* _SCRATCH156_0, 0x790 */
uint32_t scratch157; /* _SCRATCH157_0, 0x794 */
uint32_t scratch158; /* _SCRATCH158_0, 0x798 */
uint32_t scratch159; /* _SCRATCH159_0, 0x79c */
uint32_t scratch160; /* _SCRATCH160_0, 0x7a0 */
uint32_t scratch161; /* _SCRATCH161_0, 0x7a4 */
uint32_t scratch162; /* _SCRATCH162_0, 0x7a8 */
uint32_t scratch163; /* _SCRATCH163_0, 0x7ac */
uint32_t scratch164; /* _SCRATCH164_0, 0x7b0 */
uint32_t scratch165; /* _SCRATCH165_0, 0x7b4 */
uint32_t scratch166; /* _SCRATCH166_0, 0x7b8 */
uint32_t scratch167; /* _SCRATCH167_0, 0x7bc */
uint32_t scratch168; /* _SCRATCH168_0, 0x7c0 */
uint32_t scratch169; /* _SCRATCH169_0, 0x7c4 */
uint32_t scratch170; /* _SCRATCH170_0, 0x7c8 */
uint32_t scratch171; /* _SCRATCH171_0, 0x7cc */
uint32_t scratch172; /* _SCRATCH172_0, 0x7d0 */
uint32_t scratch173; /* _SCRATCH173_0, 0x7d4 */
uint32_t scratch174; /* _SCRATCH174_0, 0x7d8 */
uint32_t scratch175; /* _SCRATCH175_0, 0x7dc */
uint32_t scratch176; /* _SCRATCH176_0, 0x7e0 */
uint32_t scratch177; /* _SCRATCH177_0, 0x7e4 */
uint32_t scratch178; /* _SCRATCH178_0, 0x7e8 */
uint32_t scratch179; /* _SCRATCH179_0, 0x7ec */
uint32_t scratch180; /* _SCRATCH180_0, 0x7f0 */
uint32_t scratch181; /* _SCRATCH181_0, 0x7f4 */
uint32_t scratch182; /* _SCRATCH182_0, 0x7f8 */
uint32_t scratch183; /* _SCRATCH183_0, 0x7fc */
uint32_t scratch184; /* _SCRATCH184_0, 0x800 */
uint32_t scratch185; /* _SCRATCH185_0, 0x804 */
uint32_t scratch186; /* _SCRATCH186_0, 0x808 */
uint32_t scratch187; /* _SCRATCH187_0, 0x80c */
uint32_t scratch188; /* _SCRATCH188_0, 0x810 */
uint32_t scratch189; /* _SCRATCH189_0, 0x814 */
uint32_t scratch190; /* _SCRATCH190_0, 0x818 */
uint32_t scratch191; /* _SCRATCH191_0, 0x81c */
uint32_t scratch192; /* _SCRATCH192_0, 0x820 */
uint32_t scratch193; /* _SCRATCH193_0, 0x824 */
uint32_t scratch194; /* _SCRATCH194_0, 0x828 */
uint32_t scratch195; /* _SCRATCH195_0, 0x82c */
uint32_t scratch196; /* _SCRATCH196_0, 0x830 */
uint32_t scratch197; /* _SCRATCH197_0, 0x834 */
uint32_t scratch198; /* _SCRATCH198_0, 0x838 */
uint32_t scratch199; /* _SCRATCH199_0, 0x83c */
uint32_t scratch200; /* _SCRATCH200_0, 0x840 */
uint32_t scratch201; /* _SCRATCH201_0, 0x844 */
uint32_t scratch202; /* _SCRATCH202_0, 0x848 */
uint32_t scratch203; /* _SCRATCH203_0, 0x84c */
uint32_t scratch204; /* _SCRATCH204_0, 0x850 */
uint32_t scratch205; /* _SCRATCH205_0, 0x854 */
uint32_t scratch206; /* _SCRATCH206_0, 0x858 */
uint32_t scratch207; /* _SCRATCH207_0, 0x85c */
uint32_t scratch208; /* _SCRATCH208_0, 0x860 */
uint32_t scratch209; /* _SCRATCH209_0, 0x864 */
uint32_t scratch210; /* _SCRATCH210_0, 0x868 */
uint32_t scratch211; /* _SCRATCH211_0, 0x86c */
uint32_t scratch212; /* _SCRATCH212_0, 0x870 */
uint32_t scratch213; /* _SCRATCH213_0, 0x874 */
uint32_t scratch214; /* _SCRATCH214_0, 0x878 */
uint32_t scratch215; /* _SCRATCH215_0, 0x87c */
uint32_t scratch216; /* _SCRATCH216_0, 0x880 */
uint32_t scratch217; /* _SCRATCH217_0, 0x884 */
uint32_t scratch218; /* _SCRATCH218_0, 0x888 */
uint32_t scratch219; /* _SCRATCH219_0, 0x88c */
uint32_t scratch220; /* _SCRATCH220_0, 0x890 */
uint32_t scratch221; /* _SCRATCH221_0, 0x894 */
uint32_t scratch222; /* _SCRATCH222_0, 0x898 */
uint32_t scratch223; /* _SCRATCH223_0, 0x89c */
uint32_t scratch224; /* _SCRATCH224_0, 0x8a0 */
uint32_t scratch225; /* _SCRATCH225_0, 0x8a4 */
uint32_t scratch226; /* _SCRATCH226_0, 0x8a8 */
uint32_t scratch227; /* _SCRATCH227_0, 0x8ac */
uint32_t scratch228; /* _SCRATCH228_0, 0x8b0 */
uint32_t scratch229; /* _SCRATCH229_0, 0x8b4 */
uint32_t scratch230; /* _SCRATCH230_0, 0x8b8 */
uint32_t scratch231; /* _SCRATCH231_0, 0x8bc */
uint32_t scratch232; /* _SCRATCH232_0, 0x8c0 */
uint32_t scratch233; /* _SCRATCH233_0, 0x8c4 */
uint32_t scratch234; /* _SCRATCH234_0, 0x8c8 */
uint32_t scratch235; /* _SCRATCH235_0, 0x8cc */
uint32_t scratch236; /* _SCRATCH236_0, 0x8d0 */
uint32_t scratch237; /* _SCRATCH237_0, 0x8d4 */
uint32_t scratch238; /* _SCRATCH238_0, 0x8d8 */
uint32_t scratch239; /* _SCRATCH239_0, 0x8dc */
uint32_t scratch240; /* _SCRATCH240_0, 0x8e0 */
uint32_t scratch241; /* _SCRATCH241_0, 0x8e4 */
uint32_t scratch242; /* _SCRATCH242_0, 0x8e8 */
uint32_t scratch243; /* _SCRATCH243_0, 0x8ec */
uint32_t scratch244; /* _SCRATCH244_0, 0x8f0 */
uint32_t scratch245; /* _SCRATCH245_0, 0x8f4 */
uint32_t scratch246; /* _SCRATCH246_0, 0x8f8 */
uint32_t scratch247; /* _SCRATCH247_0, 0x8fc */
uint32_t scratch248; /* _SCRATCH248_0, 0x900 */
uint32_t scratch249; /* _SCRATCH249_0, 0x904 */
uint32_t scratch250; /* _SCRATCH250_0, 0x908 */
uint32_t scratch251; /* _SCRATCH251_0, 0x90c */
uint32_t scratch252; /* _SCRATCH252_0, 0x910 */
uint32_t scratch253; /* _SCRATCH253_0, 0x914 */
uint32_t scratch254; /* _SCRATCH254_0, 0x918 */
uint32_t scratch255; /* _SCRATCH255_0, 0x91c */
uint32_t scratch256; /* _SCRATCH256_0, 0x920 */
uint32_t scratch257; /* _SCRATCH257_0, 0x924 */
uint32_t scratch258; /* _SCRATCH258_0, 0x928 */
uint32_t scratch259; /* _SCRATCH259_0, 0x92c */
uint32_t scratch260; /* _SCRATCH260_0, 0x930 */
uint32_t scratch261; /* _SCRATCH261_0, 0x934 */
uint32_t scratch262; /* _SCRATCH262_0, 0x938 */
uint32_t scratch263; /* _SCRATCH263_0, 0x93c */
uint32_t scratch264; /* _SCRATCH264_0, 0x940 */
uint32_t scratch265; /* _SCRATCH265_0, 0x944 */
uint32_t scratch266; /* _SCRATCH266_0, 0x948 */
uint32_t scratch267; /* _SCRATCH267_0, 0x94c */
uint32_t scratch268; /* _SCRATCH268_0, 0x950 */
uint32_t scratch269; /* _SCRATCH269_0, 0x954 */
uint32_t scratch270; /* _SCRATCH270_0, 0x958 */
uint32_t scratch271; /* _SCRATCH271_0, 0x95c */
uint32_t scratch272; /* _SCRATCH272_0, 0x960 */
uint32_t scratch273; /* _SCRATCH273_0, 0x964 */
uint32_t scratch274; /* _SCRATCH274_0, 0x968 */
uint32_t scratch275; /* _SCRATCH275_0, 0x96c */
uint32_t scratch276; /* _SCRATCH276_0, 0x970 */
uint32_t scratch277; /* _SCRATCH277_0, 0x974 */
uint32_t scratch278; /* _SCRATCH278_0, 0x978 */
uint32_t scratch279; /* _SCRATCH279_0, 0x97c */
uint32_t scratch280; /* _SCRATCH280_0, 0x980 */
uint32_t scratch281; /* _SCRATCH281_0, 0x984 */
uint32_t scratch282; /* _SCRATCH282_0, 0x988 */
uint32_t scratch283; /* _SCRATCH283_0, 0x98c */
uint32_t scratch284; /* _SCRATCH284_0, 0x990 */
uint32_t scratch285; /* _SCRATCH285_0, 0x994 */
uint32_t scratch286; /* _SCRATCH286_0, 0x998 */
uint32_t scratch287; /* _SCRATCH287_0, 0x99c */
uint32_t scratch288; /* _SCRATCH288_0, 0x9a0 */
uint32_t scratch289; /* _SCRATCH289_0, 0x9a4 */
uint32_t scratch290; /* _SCRATCH290_0, 0x9a8 */
uint32_t scratch291; /* _SCRATCH291_0, 0x9ac */
uint32_t scratch292; /* _SCRATCH292_0, 0x9b0 */
uint32_t scratch293; /* _SCRATCH293_0, 0x9b4 */
uint32_t scratch294; /* _SCRATCH294_0, 0x9b8 */
uint32_t scratch295; /* _SCRATCH295_0, 0x9bc */
uint32_t scratch296; /* _SCRATCH296_0, 0x9c0 */
uint32_t scratch297; /* _SCRATCH297_0, 0x9c4 */
uint32_t scratch298; /* _SCRATCH298_0, 0x9c8 */
uint32_t scratch299; /* _SCRATCH299_0, 0x9cc */
uint32_t _0x9d0[50];
uint32_t secure_scratch80; /* _SECURE_SCRATCH80_0, 0xa98 */
uint32_t secure_scratch81; /* _SECURE_SCRATCH81_0, 0xa9c */
uint32_t secure_scratch82; /* _SECURE_SCRATCH82_0, 0xaa0 */
uint32_t secure_scratch83; /* _SECURE_SCRATCH83_0, 0xaa4 */
uint32_t secure_scratch84; /* _SECURE_SCRATCH84_0, 0xaa8 */
uint32_t secure_scratch85; /* _SECURE_SCRATCH85_0, 0xaac */
uint32_t secure_scratch86; /* _SECURE_SCRATCH86_0, 0xab0 */
uint32_t secure_scratch87; /* _SECURE_SCRATCH87_0, 0xab4 */
uint32_t secure_scratch88; /* _SECURE_SCRATCH88_0, 0xab8 */
uint32_t secure_scratch89; /* _SECURE_SCRATCH89_0, 0xabc */
uint32_t secure_scratch90; /* _SECURE_SCRATCH90_0, 0xac0 */
uint32_t secure_scratch91; /* _SECURE_SCRATCH91_0, 0xac4 */
uint32_t secure_scratch92; /* _SECURE_SCRATCH92_0, 0xac8 */
uint32_t secure_scratch93; /* _SECURE_SCRATCH93_0, 0xacc */
uint32_t secure_scratch94; /* _SECURE_SCRATCH94_0, 0xad0 */
uint32_t secure_scratch95; /* _SECURE_SCRATCH95_0, 0xad4 */
uint32_t secure_scratch96; /* _SECURE_SCRATCH96_0, 0xad8 */
uint32_t secure_scratch97; /* _SECURE_SCRATCH97_0, 0xadc */
uint32_t secure_scratch98; /* _SECURE_SCRATCH98_0, 0xae0 */
uint32_t secure_scratch99; /* _SECURE_SCRATCH99_0, 0xae4 */
uint32_t secure_scratch100; /* _SECURE_SCRATCH100_0, 0xae8 */
uint32_t secure_scratch101; /* _SECURE_SCRATCH101_0, 0xaec */
uint32_t secure_scratch102; /* _SECURE_SCRATCH102_0, 0xaf0 */
uint32_t secure_scratch103; /* _SECURE_SCRATCH103_0, 0xaf4 */
uint32_t secure_scratch104; /* _SECURE_SCRATCH104_0, 0xaf8 */
uint32_t secure_scratch105; /* _SECURE_SCRATCH105_0, 0xafc */
uint32_t secure_scratch106; /* _SECURE_SCRATCH106_0, 0xb00 */
uint32_t secure_scratch107; /* _SECURE_SCRATCH107_0, 0xb04 */
uint32_t secure_scratch108; /* _SECURE_SCRATCH108_0, 0xb08 */
uint32_t secure_scratch109; /* _SECURE_SCRATCH109_0, 0xb0c */
uint32_t secure_scratch110; /* _SECURE_SCRATCH110_0, 0xb10 */
uint32_t secure_scratch111; /* _SECURE_SCRATCH111_0, 0xb14 */
uint32_t secure_scratch112; /* _SECURE_SCRATCH112_0, 0xb18 */
uint32_t secure_scratch113; /* _SECURE_SCRATCH113_0, 0xb1c */
uint32_t secure_scratch114; /* _SECURE_SCRATCH114_0, 0xb20 */
uint32_t secure_scratch115; /* _SECURE_SCRATCH115_0, 0xb24 */
uint32_t secure_scratch116; /* _SECURE_SCRATCH116_0, 0xb28 */
uint32_t secure_scratch117; /* _SECURE_SCRATCH117_0, 0xb2c */
uint32_t secure_scratch118; /* _SECURE_SCRATCH118_0, 0xb30 */
uint32_t secure_scratch119; /* _SECURE_SCRATCH119_0, 0xb34 */
uint32_t secure_scratch120; /* _SECURE_SCRATCH120_0, 0xb38 */
uint32_t secure_scratch121; /* _SECURE_SCRATCH121_0, 0xb3c */
uint32_t secure_scratch122; /* _SECURE_SCRATCH122_0, 0xb40 */
uint32_t secure_scratch123; /* _SECURE_SCRATCH123_0, 0xb44 */
uint32_t led_breathing_ctrl; /* _LED_BREATHING_CTRL_0, 0xb48 */
uint32_t led_breathing_counter0; /* _LED_BREATHING_COUNTER0_0, 0xb4c */
uint32_t led_breathing_counter1; /* _LED_BREATHING_COUNTER1_0, 0xb50 */
uint32_t led_breathing_counter2; /* _LED_BREATHING_COUNTER2_0, 0xb54 */
uint32_t led_breathing_counter3; /* _LED_BREATHING_COUNTER3_0, 0xb58 */
uint32_t led_breathing_status; /* _LED_BREATHING_STATUS_0, 0xb5c */
uint32_t _0xb60[2];
uint32_t secure_scratch124; /* _SECURE_SCRATCH124_0, 0xb68 */
uint32_t secure_scratch125; /* _SECURE_SCRATCH125_0, 0xb6c */
uint32_t secure_scratch126; /* _SECURE_SCRATCH126_0, 0xb70 */
uint32_t secure_scratch127; /* _SECURE_SCRATCH127_0, 0xb74 */
uint32_t secure_scratch128; /* _SECURE_SCRATCH128_0, 0xb78 */
uint32_t secure_scratch129; /* _SECURE_SCRATCH129_0, 0xb7c */
uint32_t secure_scratch130; /* _SECURE_SCRATCH130_0, 0xb80 */
uint32_t secure_scratch131; /* _SECURE_SCRATCH131_0, 0xb84 */
uint32_t secure_scratch132; /* _SECURE_SCRATCH132_0, 0xb88 */
uint32_t secure_scratch133; /* _SECURE_SCRATCH133_0, 0xb8c */
uint32_t secure_scratch134; /* _SECURE_SCRATCH134_0, 0xb90 */
uint32_t secure_scratch135; /* _SECURE_SCRATCH135_0, 0xb94 */
uint32_t secure_scratch136; /* _SECURE_SCRATCH136_0, 0xb98 */
uint32_t secure_scratch137; /* _SECURE_SCRATCH137_0, 0xb9c */
uint32_t secure_scratch138; /* _SECURE_SCRATCH138_0, 0xba0 */
uint32_t secure_scratch139; /* _SECURE_SCRATCH139_0, 0xba4 */
uint32_t _0xba8[2];
uint32_t sec_disable_ns; /* _SEC_DISABLE_NS_0, 0xbb0 */
uint32_t sec_disable2_ns; /* _SEC_DISABLE2_NS_0, 0xbb4 */
uint32_t sec_disable3_ns; /* _SEC_DISABLE3_NS_0, 0xbb8 */
uint32_t sec_disable4_ns; /* _SEC_DISABLE4_NS_0, 0xbbc */
uint32_t sec_disable5_ns; /* _SEC_DISABLE5_NS_0, 0xbc0 */
uint32_t sec_disable6_ns; /* _SEC_DISABLE6_NS_0, 0xbc4 */
uint32_t sec_disable7_ns; /* _SEC_DISABLE7_NS_0, 0xbc8 */
uint32_t sec_disable8_ns; /* _SEC_DISABLE8_NS_0, 0xbcc */
uint32_t sec_disable9_ns; /* _SEC_DISABLE9_NS_0, 0xbd0 */
uint32_t sec_disable10_ns; /* _SEC_DISABLE10_NS_0, 0xbd4 */
uint32_t _0xbd8[4];
uint32_t tzram_pwr_cntrl; /* _TZRAM_PWR_CNTRL_0, 0xbe8 */
uint32_t tzram_sec_disable; /* _TZRAM_SEC_DISABLE_0, 0xbec */
uint32_t tzram_non_sec_disable; /* _TZRAM_NON_SEC_DISABLE_0, 0xbf0 */
} tegra_pmc_t;
static inline volatile tegra_pmc_t *pmc_get_regs(void)
{
return (volatile tegra_pmc_t *)PMC_BASE;
}
#endif

0
fusee/fusee-primary/src/preprocessor.h → fusee/fusee-primary/fusee-primary-main/src/preprocessor.h
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76
fusee/fusee-primary/fusee-primary-main/src/reboot_start.s Normal file
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@ -0,0 +1,76 @@
/*
* Copyright (c) 2018-2020 Atmosphère-NX
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
.macro CLEAR_GPR_REG_ITER
mov r\@, #0
.endm
.section .reboot.start, "ax", %progbits
.arm
.align 5
.global reboot_start
.type reboot_start, %function
reboot_start:
/* Switch to system mode, mask all interrupts, clear all flags */
msr cpsr_cxsf, #0xDF
/* Relocate reboot start to 0x4003E000. */
ldr r0, =0x4003E000
adr r1, reboot_start
cmp r0, r1
beq 1f
mov r2, #0x1000
0:
ldmia r1!, {r5-r12}
stmia r0!, {r5-r12}
subs r2, #0x20
bne 0b
ldr r0, =0x4003E000
adr r1, reboot_start
adr r2, 1f
sub r2, r2, r1
add r2, r2, r0
bx r2
1:
/* Restore our low iram code. */
ldr r0, =0x40008000
ldr r1, =0x40030000
mov r2, #0x8000
0:
ldmia r1!, {r5-r12}
stmia r0!, {r5-r12}
subs r2, #0x20
bne 0b
/* Restore our upper stub code. */
ldr r0, =0x40010000
ldr r1, =0x4003D000
mov r2, #0x1000
0:
ldmia r1!, {r5-r12}
stmia r0!, {r5-r12}
subs r2, #0x20
bne 0b
/* Jump to start. */
ldr r0, =0x40008000
bx r0
0: b 0b

3366
fusee/fusee-primary/fusee-primary-main/src/sdram.c Normal file
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6
fusee/fusee-primary/src/sdram.h → fusee/fusee-primary/fusee-primary-main/src/sdram.h
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@ -18,8 +18,8 @@
#ifndef FUSEE_SDRAM_H_
#define FUSEE_SDRAM_H_
void sdram_init();
const void *sdram_get_params();
void sdram_lp0_save_params(const void *params);
void sdram_init(void);
const void *sdram_get_params(uint32_t dram_id);
void sdram_save_params(const void *save_params);
#endif

3560
fusee/fusee-primary/fusee-primary-main/src/sdram.inl Normal file
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