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https://github.com/Atmosphere-NX/Atmosphere.git
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creating an enum for all used MC registers
replacing all MC_REG hex values with its enum
This commit is contained in:
Resaec
parent
dba0d62ef7
commit
5565a2d131
2 changed files with 146 additions and 51 deletions
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@ -66,21 +66,29 @@ void bootup_misc_mmio(void) {
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APBDEV_PMC_DPD_ENABLE_0 = 0;
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/* Setup MC. */
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/* TODO: What are these MC reg writes? */
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MAKE_MC_REG(0x984) = 1;
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MAKE_MC_REG(0x648) = 0;
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MAKE_MC_REG(0x64C) = 0;
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MAKE_MC_REG(0x650) = 1;
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MAKE_MC_REG(0x670) = 0;
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MAKE_MC_REG(0x674) = 0;
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MAKE_MC_REG(0x678) = 1;
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MAKE_MC_REG(0x9A0) = 0;
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MAKE_MC_REG(0x9A4) = 0;
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MAKE_MC_REG(0x9A8) = 0;
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MAKE_MC_REG(0x9AC) = 1;
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MC_SECURITY_CFG0_0 = 0;
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MC_SECURITY_CFG1_0 = 0;
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MC_SECURITY_CFG3_0 = 3;
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MAKE_MC_REG(MC_REGISTER_VIDEO_PROTECT_GPU_OVERRIDE_0_0) = 1;
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/* undefined in reference manual */
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MAKE_MC_REG(MC_REGISTER_0x648) = 0;
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MAKE_MC_REG(MC_REGISTER_0x64C) = 0;
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MAKE_MC_REG(MC_REGISTER_0x650) = 1;
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/* disable SEC carveout */
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MAKE_MC_REG(MC_REGISTER_SEC_CARVEOUT_BOM_0) = 0;
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MAKE_MC_REG(MC_REGISTER_SEC_CARVEOUT_SIZE_MB_0) = 0;
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MAKE_MC_REG(MC_REGISTER_SEC_CARVEOUT_REG_CTRL_0) = 1;
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/* disable MTS carveout */
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MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_BOM_0) = 0;
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MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_SIZE_MB_0) = 0;
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MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_ADR_HI_0) = 0;
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MAKE_MC_REG(MC_REGISTER_MTS_CARVEOUT_REG_CTRL_0) = 1;
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/* disable security carveout - SECURITY_CFG0_0, CFG1_0, CFG3_0 */
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MAKE_MC_REG(MC_REGISTER_SECURITY_BOM) = 0;
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MAKE_MC_REG(MC_REGISTER_SECURITY_SIZE_MB) = 0;
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MAKE_MC_REG(MC_REGISTER_SECURITY_BOM_HI) = 0x11;
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configure_default_carveouts();
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/* Mark registers secure world only. */
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@ -102,33 +110,45 @@ void bootup_misc_mmio(void) {
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/* Starting on 4.x on non-dev units, mark SDMMC1 secure only. */
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sec_disable_2 |= 1;
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}
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = sec_disable_1;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
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/* reset translation tables to allow all */
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MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_0_0) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_1_0) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_2_0) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_3_0) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_REGISTER_SMMU_TRANSLATION_ENABLE_4_0) = 0xFFFFFFFF;
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MAKE_MC_REG(MC_REGISTER_0x38) = 0;
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MAKE_MC_REG(MC_REGISTER_0x3C) = 0;
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/* disable stall calls after ring1 and ring3 requests */
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MAKE_MC_REG(MC_REGISTER_EMEM_ARB_RING1_THROTTLE_0) = 0;
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MAKE_MC_REG(MC_REGISTER_EMEM_ARB_RING3_THROTTLE_0) = 0;
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MAKE_MC_REG(MC_REGISTER_EMEM_ARB_OVERRIDE_0) = 0; /* disable overrides */
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MAKE_MC_REG(MC_REGISTER_EMEM_ARB_RSV_0) = 0; /* null reserved register */
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MAKE_MC_REG(MC_REGISTER_0xF0) = 0;
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/* disable clock-enable overrides */
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MAKE_MC_REG(MC_REGISTER_CLKEN_OVERRIDE_0) = 0;
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/* reset PTB, TLB and PTC */
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MAKE_MC_REG(MC_REGISTER_SMMU_PTB_DATA_0) = 0;
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MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0) = 0x30000030;
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MAKE_MC_REG(MC_REGISTER_SMMU_PTC_CONFIG_0) = 0x2800003F;
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/* TODO: What are these MC reg writes? */
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MAKE_MC_REG(0x228) = 0xFFFFFFFF;
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MAKE_MC_REG(0x22C) = 0xFFFFFFFF;
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MAKE_MC_REG(0x230) = 0xFFFFFFFF;
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MAKE_MC_REG(0x234) = 0xFFFFFFFF;
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MAKE_MC_REG(0xB98) = 0xFFFFFFFF;
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MAKE_MC_REG(0x038) = 0;
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MAKE_MC_REG(0x03C) = 0;
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MAKE_MC_REG(0x0E0) = 0;
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MAKE_MC_REG(0x0E4) = 0;
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MAKE_MC_REG(0x0E8) = 0;
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MAKE_MC_REG(0x0EC) = 0;
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MAKE_MC_REG(0x0F0) = 0;
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MAKE_MC_REG(0x0F4) = 0;
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MAKE_MC_REG(0x020) = 0;
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MAKE_MC_REG(0x014) = 0x30000030;
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MAKE_MC_REG(0x018) = 0x2800003F;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x034) = 0;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x030) = 0;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x010) = 1;
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(void)(MAKE_MC_REG(0x014));
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(void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
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MAKE_MC_REG(MC_REGISTER_SMMU_PTC_FLUSH_0) = 0;
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(void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
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MAKE_MC_REG(MC_REGISTER_SMMU_TLB_FLUSH_0) = 0;
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(void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
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MAKE_MC_REG(MC_REGISTER_SMMU_CONFIG_0) = 0x1; /* enable SMMU */
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(void)(MAKE_MC_REG(MC_REGISTER_SMMU_TLB_CONFIG_0));
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/* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */
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uint32_t reset_vec = TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_WARMBOOT_CRT0_AND_MAIN);
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@ -168,19 +188,20 @@ void bootup_misc_mmio(void) {
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g_has_booted_up = true;
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} else if (exosphere_get_target_firmware() < EXOSPHERE_TARGET_FIRMWARE_400) {
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/* TODO: What are these MC reg writes? */
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MAKE_MC_REG(0x65C) = 0xFFFFF000;
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MAKE_MC_REG(0x660) = 0;
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MAKE_MC_REG(0x964) |= 1;
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MAKE_MC_REG(MC_REGISTER_0x65C) = 0xFFFFF000;
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MAKE_MC_REG(MC_REGISTER_0x660) = 0;
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MAKE_MC_REG(MC_REGISTER_IRAM_REG_CTRL_0) |= 1; /* overlap at 18.11.1.86 and 18.11.1.87 - lock write access to IRAM and EMEM registers */
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CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
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}
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}
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void setup_4x_mmio(void) {
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/* TODO: What are these MC reg writes? */
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MAKE_MC_REG(0x65C) = 0xFFFFF000;
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MAKE_MC_REG(0x660) = 0;
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MAKE_MC_REG(0x964) |= 1;
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MAKE_MC_REG(MC_REGISTER_0x65C) = 0xFFFFF000;
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MAKE_MC_REG(MC_REGISTER_0x660) = 0;
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MAKE_MC_REG(MC_REGISTER_IRAM_REG_CTRL_0) |= 1; /* as above, lock write access to IRAM and EMEM registers */
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CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
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/* TODO: What are these PMC scratch writes? */
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APBDEV_PMC_SECURE_SCRATCH51_0 = (APBDEV_PMC_SECURE_SCRATCH51_0 & 0xFFFF8000) | 0x4000;
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APBDEV_PMC_SECURE_SCRATCH16_0 &= 0x3FFFFFFF;
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@ -14,14 +14,14 @@ static inline uintptr_t get_mc_base(void) {
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#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
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#define MC_SMMU_PTB_ASID_0 MAKE_MC_REG(0x01C)
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#define MC_SMMU_PTB_DATA_0 MAKE_MC_REG(0x020)
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#define MC_SMMU_AVPC_ASID_0 MAKE_MC_REG(0x23C)
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#define MC_SMMU_PPCS1_ASID_0 MAKE_MC_REG(0x298)
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#define MC_SMMU_PTB_ASID_0 MAKE_MC_REG(MC_REGISTER_SMMU_PTB_ASID_0)
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#define MC_SMMU_PTB_DATA_0 MAKE_MC_REG(MC_REGISTER_SMMU_PTB_DATA_0)
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#define MC_SMMU_AVPC_ASID_0 MAKE_MC_REG(MC_REGISTER_SMMU_AVPC_ASID_0)
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#define MC_SMMU_PPCS1_ASID_0 MAKE_MC_REG(MC_REGISTER_SMMU_PPCS1_ASID_0)
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#define MC_SECURITY_CFG0_0 MAKE_MC_REG(0x070)
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#define MC_SECURITY_CFG1_0 MAKE_MC_REG(0x074)
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#define MC_SECURITY_CFG3_0 MAKE_MC_REG(0x9BC)
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#define MC_SECURITY_CFG0_0 MAKE_MC_REG(MC_REGISTER_SECURITY_BOM)
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#define MC_SECURITY_CFG1_0 MAKE_MC_REG(MC_REGISTER_SECURITY_SIZE_MB)
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#define MC_SECURITY_CFG3_0 MAKE_MC_REG(MC_REGISTER_SECURITY_BOM_HI)
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#define CARVEOUT_ID_MIN 1
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@ -47,6 +47,80 @@ typedef struct {
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uint8_t padding[0x28];
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} security_carveout_t;
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/* 18.11.1 MC Registers */
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typedef enum {
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MC_REGISTER_SMMU_CONFIG_0 = 0x10,
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MC_REGISTER_SMMU_TLB_CONFIG_0 = 0x14, /* Controls usage of the TLB */
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MC_REGISTER_SMMU_PTC_CONFIG_0 = 0x18, /* Controls usage of the PTC */
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MC_REGISTER_SMMU_PTB_ASID_0 = 0x1C,
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MC_REGISTER_SMMU_PTB_DATA_0 = 0x20,
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MC_REGISTER_SMMU_TLB_FLUSH_0 = 0x30,
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MC_REGISTER_SMMU_PTC_FLUSH_0 = 0x34,
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MC_REGISTER_0x38 = 0x38,
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MC_REGISTER_0x3C = 0x3C,
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/* SECURITY_BOM is the base of the secured region, limited to MB granularity.
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This must point to a region of the physical address map allocated to EMEM for it to be effective; the MC cannot secure address space it does not own. (In other words, this is an absolute address, not an offset.)
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Above is the list of clients with the TrustZone-security access. [18.11.1.20]
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Note that AXICIF clients will adhere to the standard AXI protocol "aprot[1]==0" indication for secure requests. */
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MC_REGISTER_SECURITY_BOM = 0x70,
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MC_REGISTER_SECURITY_CFG0_0 = MC_REGISTER_SECURITY_BOM,
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MC_REGISTER_SECURITY_SIZE_MB = 0x74, /* SECURITY_SIZE_MB is the size, in megabytes, of the secured region. If set to 0, the security check in MC is disabled */
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MC_REGISTER_SECURITY_CFG1_0 = MC_REGISTER_SECURITY_SIZE_MB,
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MC_REGISTER_EMEM_ARB_RING1_THROTTLE_0 = 0xE0,
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MC_REGISTER_EMEM_ARB_RING3_THROTTLE_0 = 0xE4,
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MC_REGISTER_EMEM_ARB_OVERRIDE_0 = 0xE8,
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MC_REGISTER_EMEM_ARB_RSV_0 = 0xEC,
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MC_REGISTER_0xF0 = 0xF0,
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MC_REGISTER_CLKEN_OVERRIDE_0 = 0xF4,
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MC_REGISTER_SMMU_TRANSLATION_ENABLE_0_0 = 0x228,
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MC_REGISTER_SMMU_TRANSLATION_ENABLE_1_0 = 0x22C,
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MC_REGISTER_SMMU_TRANSLATION_ENABLE_2_0 = 0x230,
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MC_REGISTER_SMMU_TRANSLATION_ENABLE_3_0 = 0x234,
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MC_REGISTER_SMMU_AVPC_ASID_0 = 0x23C,
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MC_REGISTER_SMMU_PPCS1_ASID_0 = 0x298,
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MC_REGISTER_0x648 = 0x648,
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MC_REGISTER_0x64C = 0x64C,
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MC_REGISTER_0x650 = 0x650,
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MC_REGISTER_0x65C = 0x65C,
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MC_REGISTER_0x660 = 0x660,
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MC_REGISTER_IRAM_REG_CTRL_0 = 0x964,
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MC_REGISTER_EMEM_CFG_ACCESS_CTRL_0 = MC_REGISTER_IRAM_REG_CTRL_0,
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MC_REGISTER_SEC_CARVEOUT_BOM_0 = 0x670, /* [PMC_SECURE] Base address for the SEC carveout address space */
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MC_REGISTER_SEC_CARVEOUT_SIZE_MB_0 = 0x674, /* [PMC_SECURE] SEC_CARVEOUT_SIZE_MB is the size, in megabytes, of the SEC carveout region. If set to 0, the security check in MC is disabled */
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/* [PMC_SECURE] Sticky bit to control the writes to the other Sec Carveout aperture registers
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0 = Enabled
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1 = Disabled */
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MC_REGISTER_SEC_CARVEOUT_REG_CTRL_0 = 0x678,
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MC_REGISTER_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x984,
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MC_REGISTER_MTS_CARVEOUT_BOM_0 = 0x9A0,
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MC_REGISTER_MTS_CARVEOUT_SIZE_MB_0 = 0x9A4,
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MC_REGISTER_MTS_CARVEOUT_ADR_HI_0 = 0x9A8,
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/* MTS_CARVEOUT_WRITE_ACCESS
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0 = Enabled
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1 = Disabled */
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MC_REGISTER_MTS_CARVEOUT_REG_CTRL_0 = 0x9AC,
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/* Base Address Higher Bits
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SECURITY_BOM_HI has the higher address bits beyond 32 bits of the
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base of the secured region, limited to MB granularity */
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MC_REGISTER_SECURITY_BOM_HI = 0x9BC,
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MC_REGISTER_SECURITY_CFG3_0 = MC_REGISTER_SECURITY_BOM_HI,
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MC_REGISTER_SMMU_TRANSLATION_ENABLE_4_0 = 0xB98
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} MC_REGISTER;
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volatile security_carveout_t *get_carveout_by_id(unsigned int carveout);
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void configure_default_carveouts(void);
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