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adding register enumerators for SMMU_TLB_CONFIG, SMMU_PTC_CONFIG, SMMU_PTB_DATA, SMMU_AVPC_ASID and SMMU_PPCS1_ASID

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refactoring mc_register writes where posible
This commit is contained in:
Resaec 2018-04-28 06:21:14 +02:00
parent 2095c633aa
commit 5d97563140
2 changed files with 55 additions and 6 deletions
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12
exosphere/src/bootup.c
View file

@ -141,8 +141,8 @@ void bootup_misc_mmio(void) {
/* reset PTB, TLB and PTC */
mc_register->SMMU_PTB_DATA_0 = 0;
mc_register->SMMU_TLB_CONFIG_0 = 0x30000030;
mc_register->SMMU_PTC_CONFIG_0 = 0x2800003F;
mc_register->SMMU_TLB_CONFIG_0 = SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION | SMMU_TLB_CONFIG_HIT_UNDER_MISS | 0x30; /* reset to default - 0x30 => TLB_ACTIVE_LINES */
mc_register->SMMU_PTC_CONFIG_0 = SMMU_PTC_CONFIG_CACHE_ENABLE | 0x8000000 | 0x3F; /* reset to default, except PTC_LINE_MASK - 0x8000000 = 0x8 << 27 => PTC_REQ_LIMIT - 0x37 => PTC_INDEX_MAP */
/* TODO: What are these MC reg writes? */
(void)(mc_register->SMMU_TLB_CONFIG_0);
@ -238,10 +238,10 @@ void setup_4x_mmio(void) {
AHB_ARBITRATION_DISABLE_0 |= 2;
/* Set SMMU for BPMP/APB-DMA to point to TZRAM. */
mc_register->SMMU_PTB_ASID_0 = 1;
mc_register->SMMU_PTB_DATA_0 = 0x70012;
mc_register->SMMU_AVPC_ASID_0 = 0x80000001;
mc_register->SMMU_PPCS1_ASID_0 = 0x80000001;
mc_register->SMMU_PTB_ASID_0 = 0x1; /* CURRENT_ASID */
mc_register->SMMU_PTB_DATA_0 = 0x70012; /* ASID_PDE_BASE */
mc_register->SMMU_AVPC_ASID_0 = SMMU_AVPC_ASID_AVPC_SMMU_ENABLE | 0x1; /* 0x1 => AVPC_ASID */
mc_register->SMMU_PPCS1_ASID_0 = SMMU_PPCS1_ASID_PPCS1_SMMU_ENABLE | 0x1; /* 0x1 => PPCS1_ASID */
/* Wait for the BPMP to halt. */
while ((FLOW_CTLR_HALT_COP_EVENTS_0 >> 29) != 5) {

49
exosphere/src/mc.h
View file

@ -242,6 +242,55 @@ typedef struct {
uint32_t SMMU_TRANSLATION_ENABLE_4_0; /* 0xB98 */
} mc_register_t; /* 0xB98 */
/* 18.11.1.6 MC_SMMU_TLB_CONFIG_0 */
typedef enum{
/* Set the number of active lines.
Allows the TLB to be made "virtually smaller" to save power.
"Inactive" lines will never hit and never hold data
*/
SMMU_TLB_CONFIG_ACTIVE_LINES = 0x3F << 0,
SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION = 1 << 28, /* When enabled, forces round robin (RR) arbitration between TLB hit and miss FIFOs */
/* Allow hits to pass misses in the TLB.
This value may not be changed on the fly.
Ideally, this should be set before enabling the SMMU.
At the very least, the TLB needs to be flushed and traffic through the SMMU stopped before changing this value
*/
SMMU_TLB_CONFIG_HIT_UNDER_MISS = 1 << 29,
SMMU_TLB_CONFIG_STATS_TEST = 1 << 30, /* Set stats registers to all "1s" */
SMMU_TLB_CONFIG_STATS_ENABLE = 1 << 31, /* Enable TLB Hit and Miss counters */
} SMMU_TLB_CONFIG;
/* 18.11.1.7 MC_SMMU_PTC_CONFIG_0 */
typedef enum {
SMMU_PTC_CONFIG_INDEX_MAP = 0x7F << 0, /* XOR pattern for tag generation */
SMMU_PTC_CONFIG_LINE_MASK = 0xF << 8, /* XOR pattern for line generation */
SMMU_PTC_CONFIG_REQ_LIMIT = 0xF << 24, /* Limit outstanding PTC fill requests to the DRAM */
SMMU_PTC_CONFIG_CACHE_ENABLE = 1 << 29, /* Enable the PTC cache */
SMMU_PTC_CONFIG_STATS_TEST = 1 << 30, /* Set stats registers to all "1s" */
SMMU_PTC_CONFIG_STATS_ENABLE = 1 << 31 /* Enable PTC Hit and Miss counters */
} SMMU_PTC_CONFIG;
/* 18.11.1.9 MC_SMMU_PTB_DATA_0 */
typedef enum {
SSM_PTB_DATA_ASID_PDE_BASE = 0x3FFFFF << 0, /* Pointer to page of PDEs, bits [33:12] for this ASID */
SSM_PTB_DATA_ASID_NONSECURE = 1 << 29, /* if set, non-secure accesses are allowed for this ASID */
SSM_PTB_DATA_ASID_WRITABLE = 1 << 30, /* if set, writes are allowed for this ASID */
SSM_PTB_DATA_ASID_READABLE = 1 << 31 /* if set, reads are allowed for this ASID */
} SMMU_PTB_DATA;
/* 18.11.1.63 MC_SMMU_AVPC_ASID_0 */
typedef enum {
SMMU_AVPC_ASID_AVPC_ASID = 0x7F << 0, /* If translation enabled, ASID to use when va[33:32] = 0x0 */
SMMU_AVPC_ASID_AVPC_SMMU_ENABLE = 1 << 31 /* if set, translation is enabled for this client */
} SMMU_AVPC_ASID;
/* 18.11.1.79 MC_SMMU_PPCS1_ASID_0 */
typedef enum{
SMMU_PPCS1_ASID_PPCS1_ASID = 0x7F << 0, /* if set, translation is enabled for this client */
SMMU_PPCS1_ASID_PPCS1_SMMU_ENABLE = 1 << 31 /* If translation enabled, ASID to use when va[33:32] = 0x0 */
} SMMU_PPCS1_ASID;
volatile security_carveout_t *get_carveout_by_id(unsigned int carveout);
void configure_default_carveouts(void);
void configure_kernel_carveout(unsigned int carveout_id, uint64_t address, uint64_t size);