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https://github.com/Atmosphere-NX/Atmosphere.git
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refactor to typedef enum
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Resaec
parent
50339381c0
commit
b2c8ec7702
2 changed files with 70 additions and 70 deletions
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@ -85,22 +85,22 @@ void bootup_misc_mmio(void) {
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/* Mark registers secure world only. */
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/* Mark SATA_AUX, DTV, QSPI, SE, SATA, LA secure only. */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = SATA_AUX | DTV | QSPI | SE | SATA | LA;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = APB_SSER0_SATA_AUX | APB_SSER0_DTV | APB_SSER0_QSPI | APB_SSER0_SE | APB_SSER0_SATA | APB_SSER0_LA;
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/* By default, mark SPI1, SPI2, SPI3, SPI5, SPI6, I2C6 secure only. */
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uint32_t sec_disable_1 = SPI1 | SPI2 | SPI3 | SPI5 | SPI6 | I2C6;
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uint32_t sec_disable_1 = APB_SSER1_SPI1 | APB_SSER1_SPI2 | APB_SSER1_SPI3 | APB_SSER1_SPI5 | APB_SSER1_SPI6 | APB_SSER1_I2C6;
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/* By default, mark SDMMC3, DDS, DP2 secure only. */
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uint32_t sec_disable_2 = SDMMC3 | DDS |DP2;
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uint32_t sec_disable_2 = APB_SSER2_SDMMC3 | APB_SSER2_DDS | APB_SSER2_DP2;
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uint64_t hardware_type = configitem_get_hardware_type();
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if (hardware_type != 1) {
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/* Also mark I2C5 secure only, */
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sec_disable_1 |= I2C4; /* TODO: It says I2C5, but the previously used 0x20000000 is I2C4 */
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sec_disable_1 |= APB_SSER1_I2C4; /* TODO: It says I2C5, but the previously used 0x20000000 is I2C4 */
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}
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if (hardware_type != 0 && exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
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/* Starting on 4.x on non-dev units, mark UARTB, UARTC, SPI4, I2C3 secure only. */
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sec_disable_1 |= UART_B | UART_C | SPI4 | I2C3;
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sec_disable_1 |= APB_SSER1_UART_B | APB_SSER1_UART_C | APB_SSER1_SPI4 | APB_SSER1_I2C3;
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/* Starting on 4.x on non-dev units, mark SDMMC1 secure only. */
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sec_disable_2 |= SDMMC1;
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sec_disable_2 |= APB_SSER2_SDMMC1;
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}
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = sec_disable_1;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
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@ -283,8 +283,8 @@ void identity_unmap_iram_cd_tzram(void) {
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void secure_additional_devices(void) {
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 |= PMC; /* make PMC secure-only (2.x+ but see note below) */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 |= MC0 | MC1 | MCB; /* make MC0, MC1, MCB secure-only (4.x+) */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 |= APB_SSER0_PMC; /* make PMC secure-only (2.x+ but see note below) */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 |= APB_SSER1_MC0 | APB_SSER1_MC1 | APB_SSER1_MCB; /* make MC0, MC1, MCB secure-only (4.x+) */
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} else {
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/* TODO: Detect 1.x */
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}
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@ -4,82 +4,82 @@
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#include <stdint.h>
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/* APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 slaves */
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enum APB_SSER0 {
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MISC_REGS = 1 << 1, /* PP, SC1x pads and GP registers */
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SATA_AUX = 1 << 2,
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PINMUX_AUX = 1 << 3,
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APE = 1 << 4,
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typedef enum {
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APB_SSER0_MISC_REGS = 1 << 1, /* PP, SC1x pads and GP registers */
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APB_SSER0_SATA_AUX = 1 << 2,
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APB_SSER0_PINMUX_AUX = 1 << 3,
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APB_SSER0_APE = 1 << 4,
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DTV = 1 << 6,
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APB_SSER0_DTV = 1 << 6,
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PWM = 1 << 8, /* PWFM */
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QSPI = 1 << 9,
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CSITE = 1 << 10, /* Core Site */
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RTC = 1 << 11,
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APB_SSER0_PWM = 1 << 8, /* PWFM */
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APB_SSER0_QSPI = 1 << 9,
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APB_SSER0_CSITE = 1 << 10, /* Core Site */
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APB_SSER0_RTC = 1 << 11,
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PMC = 1 << 13,
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SE = 1 << 14, /* Security Engine */
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FUSE = 1 << 15,
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KFUSE = 1 << 16,
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APB_SSER0_PMC = 1 << 13,
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APB_SSER0_SE = 1 << 14, /* Security Engine */
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APB_SSER0_FUSE = 1 << 15,
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APB_SSER0_KFUSE = 1 << 16,
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UNUSED = 1 << 18, /* reserved, unused but listed as accessible */
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APB_SSER0_UNUSED = 1 << 18, /* reserved, unused but listed as accessible */
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SATA = 1 << 20,
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HDA = 1 << 21,
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LA = 1 << 22,
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ATOMICS = 1 << 23,
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CEC = 1 << 24,
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APB_SSER0_SATA = 1 << 20,
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APB_SSER0_HDA = 1 << 21,
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APB_SSER0_LA = 1 << 22,
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APB_SSER0_ATOMICS = 1 << 23,
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APB_SSER0_CEC = 1 << 24,
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STM = 1 << 29
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};
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} APB_SSER0;
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/* APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 slaves */
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enum APB_SSER1 {
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MC0 = 1 << 4,
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EMC0 = 1 << 5,
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typedef enum {
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APB_SSER1_MC0 = 1 << 4,
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APB_SSER1_EMC0 = 1 << 5,
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MC1 = 1 << 8,
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EMC1 = 1 << 9,
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MCB = 1 << 10,
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EMBC = 1 << 11,
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UART_A = 1 << 12,
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UART_B = 1 << 13,
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UART_C = 1 << 14,
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UART_D = 1 << 15,
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APB_SSER1_MC1 = 1 << 8,
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APB_SSER1_EMC1 = 1 << 9,
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APB_SSER1_MCB = 1 << 10,
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APB_SSER1_EMBC = 1 << 11,
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APB_SSER1_UART_A = 1 << 12,
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APB_SSER1_UART_B = 1 << 13,
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APB_SSER1_UART_C = 1 << 14,
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APB_SSER1_UART_D = 1 << 15,
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SPI1 = 1 << 20,
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SPI2 = 1 << 21,
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SPI3 = 1 << 22,
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SPI4 = 1 << 23,
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SPI5 = 1 << 24,
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SPI6 = 1 << 25,
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I2C1 = 1 << 26,
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I2C2 = 1 << 27,
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I2C3 = 1 << 28,
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I2C4 = 1 << 29,
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DVC = 1 << 30,
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I2C5 = 1 << 30,
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I2C6 = 1 << 31 /* this will show as negative because of the 32bit sign bit being set */
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};
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APB_SSER1_SPI1 = 1 << 20,
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APB_SSER1_SPI2 = 1 << 21,
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APB_SSER1_SPI3 = 1 << 22,
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APB_SSER1_SPI4 = 1 << 23,
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APB_SSER1_SPI5 = 1 << 24,
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APB_SSER1_SPI6 = 1 << 25,
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APB_SSER1_I2C1 = 1 << 26,
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APB_SSER1_I2C2 = 1 << 27,
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APB_SSER1_I2C3 = 1 << 28,
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APB_SSER1_I2C4 = 1 << 29,
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APB_SSER1_DVC = 1 << 30,
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APB_SSER1_I2C5 = 1 << 30,
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APB_SSER1_I2C6 = 1 << 31 /* this will show as negative because of the 32bit sign bit being set */
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} APB_SSER1;
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/* APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 slaves */
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enum APB_SSER2 {
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SDMMC1 = 1 << 0,
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SDMMC2 = 1 << 1,
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SDMMC3 = 1 << 2,
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SDMMC4 = 1 << 3,
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typedef enum {
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APB_SSER2_SDMMC1 = 1 << 0,
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APB_SSER2_SDMMC2 = 1 << 1,
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APB_SSER2_SDMMC3 = 1 << 2,
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APB_SSER2_SDMMC4 = 1 << 3,
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MIPIBIF = 1 << 7, /* reserved */
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DDS = 1 << 8,
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DP2 = 1 << 9,
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SOC_THERM = 1 << 10,
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APB2JTAG = 1 << 11,
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XUSB_HOST = 1 << 12,
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XUSB_DEV = 1 << 13,
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XUSB_PADCTL = 1 << 14,
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MIPI_CAL = 1 << 15,
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DVFS = 1 << 16
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};
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APB_SSER2_MIPIBIF = 1 << 7, /* reserved */
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APB_SSER2_DDS = 1 << 8,
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APB_SSER2_DP2 = 1 << 9,
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APB_SSER2_SOC_THERM = 1 << 10,
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APB_SSER2_APB2JTAG = 1 << 11,
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APB_SSER2_XUSB_HOST = 1 << 12,
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APB_SSER2_XUSB_DEV = 1 << 13,
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APB_SSER2_XUSB_PADCTL = 1 << 14,
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APB_SSER2_MIPI_CAL = 1 << 15,
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APB_SSER2_DVFS = 1 << 16
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} APB_SSER2;
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void bootup_misc_mmio(void);
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