mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Update AInstEmitSimdArithmetic.cs

Browse source
This commit is contained in:
LDj3SNuD 2018-04-19 22:34:36 +02:00 • committed by GitHub
parent 0c1c387f8b
commit 014624dabe
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 56 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

57
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -26,7 +26,6 @@ namespace ChocolArm64.Instruction
AILLabel LblTrue = new AILLabel();
Context.Emit(OpCodes.Dup);
Context.Emit(OpCodes.Ldc_I4_0);
Context.Emit(OpCodes.Bge_S, LblTrue);
@ -45,6 +44,11 @@ namespace ChocolArm64.Instruction
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
}
public static void Addhn_V(AILEmitterCtx Context)
{
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Add), false);
}
public static void Addp_S(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
@ -130,6 +134,42 @@ namespace ChocolArm64.Instruction
}
}
private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Elems = 8 >> Op.Size;
int ESize = 8 << Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size + 1);
Emit();
if (Round)
{
Context.EmitLdc_I8(1);
Context.EmitLsl(ESize - 1);
Context.Emit(OpCodes.Add);
}
Context.EmitLsr(ESize);
EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
}
if (Part == 0)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Fabd_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpF(Context, () =>
@ -849,6 +889,16 @@ namespace ChocolArm64.Instruction
EmitVectorUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
}
public static void Raddhn_V(AILEmitterCtx Context)
{
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Add), true);
}
public static void Rsubhn_V(AILEmitterCtx Context)
{
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), true);
}
public static void Saddw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
@ -896,6 +946,11 @@ namespace ChocolArm64.Instruction
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
}
public static void Subhn_V(AILEmitterCtx Context)
{
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), false);
}
public static void Uabd_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () => EmitAbd(Context));