diff --git a/ChocolArm64/Decoders/Cond.cs b/ChocolArm64/Decoders/Condition.cs
similarity index 94%
rename from ChocolArm64/Decoders/Cond.cs
rename to ChocolArm64/Decoders/Condition.cs
index 57e12cd609..d1aa577295 100644
--- a/ChocolArm64/Decoders/Cond.cs
+++ b/ChocolArm64/Decoders/Condition.cs
@@ -1,6 +1,6 @@
 namespace ChocolArm64.Decoders
 {
-    enum Cond
+    enum Condition
     {
         Eq   = 0,
         Ne   = 1,
diff --git a/ChocolArm64/Decoders/Decoder.cs b/ChocolArm64/Decoders/Decoder.cs
index 1d6e51df52..6c60e1fe5e 100644
--- a/ChocolArm64/Decoders/Decoder.cs
+++ b/ChocolArm64/Decoders/Decoder.cs
@@ -161,7 +161,7 @@ namespace ChocolArm64.Decoders
             //Note: On ARM32, most instructions have conditional execution,
             //so there's no "Always" (unconditional) branch like on ARM64.
             //We need to check if the condition is "Always" instead.
-            return IsAarch32Branch(op) && op.Cond >= Cond.Al;
+            return IsAarch32Branch(op) && op.Cond >= Condition.Al;
         }
 
         private static bool IsAarch32Branch(OpCode64 opCode)
diff --git a/ChocolArm64/Decoders/IOpCode32.cs b/ChocolArm64/Decoders/IOpCode32.cs
index 219a7c9ffa..3353ffe8d8 100644
--- a/ChocolArm64/Decoders/IOpCode32.cs
+++ b/ChocolArm64/Decoders/IOpCode32.cs
@@ -2,7 +2,7 @@ namespace ChocolArm64.Decoders
 {
     interface IOpCode32 : IOpCode64
     {
-        Cond Cond { get; }
+        Condition Cond { get; }
 
         uint GetPc();
     }
diff --git a/ChocolArm64/Decoders/IOpCodeCond64.cs b/ChocolArm64/Decoders/IOpCodeCond64.cs
index 9c39d63329..2c465406bd 100644
--- a/ChocolArm64/Decoders/IOpCodeCond64.cs
+++ b/ChocolArm64/Decoders/IOpCodeCond64.cs
@@ -2,6 +2,6 @@ namespace ChocolArm64.Decoders
 {
     interface IOpCodeCond64 : IOpCode64
     {
-        Cond Cond { get; }
+        Condition Cond { get; }
     }
 }
\ No newline at end of file
diff --git a/ChocolArm64/Decoders/OpCode32.cs b/ChocolArm64/Decoders/OpCode32.cs
index 0e72a8afa2..8534b78fcc 100644
--- a/ChocolArm64/Decoders/OpCode32.cs
+++ b/ChocolArm64/Decoders/OpCode32.cs
@@ -5,13 +5,13 @@ namespace ChocolArm64.Decoders
 {
     class OpCode32 : OpCode64
     {
-        public Cond Cond { get; protected set; }
+        public Condition Cond { get; protected set; }
 
         public OpCode32(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
             RegisterSize = RegisterSize.Int32;
 
-            Cond = (Cond)((uint)opCode >> 28);
+            Cond = (Condition)((uint)opCode >> 28);
         }
 
         public uint GetPc()
diff --git a/ChocolArm64/Decoders/OpCodeBImm32.cs b/ChocolArm64/Decoders/OpCodeBImm32.cs
index 0f41294d8d..127ac17473 100644
--- a/ChocolArm64/Decoders/OpCodeBImm32.cs
+++ b/ChocolArm64/Decoders/OpCodeBImm32.cs
@@ -11,14 +11,14 @@ namespace ChocolArm64.Decoders
             uint pc = GetPc();
 
             //When the codition is never, the instruction is BLX to Thumb mode.
-            if (Cond != Cond.Nv)
+            if (Cond != Condition.Nv)
             {
                 pc &= ~3u;
             }
 
             Imm = pc + DecoderHelper.DecodeImm24_2(opCode);
 
-            if (Cond == Cond.Nv)
+            if (Cond == Condition.Nv)
             {
                 long H = (opCode >> 23) & 2;
 
diff --git a/ChocolArm64/Decoders/OpCodeBImmCond64.cs b/ChocolArm64/Decoders/OpCodeBImmCond64.cs
index 227023092e..ca7df5542c 100644
--- a/ChocolArm64/Decoders/OpCodeBImmCond64.cs
+++ b/ChocolArm64/Decoders/OpCodeBImmCond64.cs
@@ -4,7 +4,7 @@ namespace ChocolArm64.Decoders
 {
     class OpCodeBImmCond64 : OpCodeBImm64, IOpCodeCond64
     {
-        public Cond Cond { get; private set; }
+        public Condition Cond { get; private set; }
 
         public OpCodeBImmCond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
@@ -17,7 +17,7 @@ namespace ChocolArm64.Decoders
                 return;
             }
 
-            Cond = (Cond)(opCode & 0xf);
+            Cond = (Condition)(opCode & 0xf);
 
             Imm = position + DecoderHelper.DecodeImmS19_2(opCode);
         }
diff --git a/ChocolArm64/Decoders/OpCodeCcmp64.cs b/ChocolArm64/Decoders/OpCodeCcmp64.cs
index f2d370b6d3..7cede5f774 100644
--- a/ChocolArm64/Decoders/OpCodeCcmp64.cs
+++ b/ChocolArm64/Decoders/OpCodeCcmp64.cs
@@ -8,7 +8,7 @@ namespace ChocolArm64.Decoders
         public    int Nzcv { get; private set; }
         protected int RmImm;
 
-        public Cond Cond { get; private set; }
+        public Condition Cond { get; private set; }
 
         public OpCodeCcmp64(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
@@ -22,7 +22,7 @@ namespace ChocolArm64.Decoders
             }
 
             Nzcv  =        (opCode >>  0) & 0xf;
-            Cond  = (Cond)((opCode >> 12) & 0xf);
+            Cond  = (Condition)((opCode >> 12) & 0xf);
             RmImm =        (opCode >> 16) & 0x1f;
 
             Rd = RegisterAlias.Zr;
diff --git a/ChocolArm64/Decoders/OpCodeCsel64.cs b/ChocolArm64/Decoders/OpCodeCsel64.cs
index d1a5a2dbee..f2ceb33800 100644
--- a/ChocolArm64/Decoders/OpCodeCsel64.cs
+++ b/ChocolArm64/Decoders/OpCodeCsel64.cs
@@ -6,12 +6,12 @@ namespace ChocolArm64.Decoders
     {
         public int Rm { get; private set; }
 
-        public Cond Cond { get; private set; }
+        public Condition Cond { get; private set; }
 
         public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
             Rm   =        (opCode >> 16) & 0x1f;
-            Cond = (Cond)((opCode >> 12) & 0xf);
+            Cond = (Condition)((opCode >> 12) & 0xf);
         }
     }
 }
\ No newline at end of file
diff --git a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
index f805b3c120..ea1e03d5a2 100644
--- a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
+++ b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs
@@ -6,12 +6,12 @@ namespace ChocolArm64.Decoders
     {
         public int Nzcv { get; private set; }
 
-        public Cond Cond { get; private set; }
+        public Condition Cond { get; private set; }
 
         public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
             Nzcv =        (opCode >>  0) & 0xf;
-            Cond = (Cond)((opCode >> 12) & 0xf);
+            Cond = (Condition)((opCode >> 12) & 0xf);
         }
     }
 }
diff --git a/ChocolArm64/Decoders/OpCodeT16.cs b/ChocolArm64/Decoders/OpCodeT16.cs
index 190b1d3ce8..005c470d1a 100644
--- a/ChocolArm64/Decoders/OpCodeT16.cs
+++ b/ChocolArm64/Decoders/OpCodeT16.cs
@@ -6,7 +6,7 @@ namespace ChocolArm64.Decoders
     {
         public OpCodeT16(Inst inst, long position, int opCode) : base(inst, position, opCode)
         {
-            Cond = Cond.Al;
+            Cond = Condition.Al;
 
             OpCodeSizeInBytes = 2;
         }
diff --git a/ChocolArm64/Instructions/InstEmitFlow.cs b/ChocolArm64/Instructions/InstEmitFlow.cs
index ea43449e63..181c6a04f7 100644
--- a/ChocolArm64/Instructions/InstEmitFlow.cs
+++ b/ChocolArm64/Instructions/InstEmitFlow.cs
@@ -102,7 +102,7 @@ namespace ChocolArm64.Instructions
             EmitBranch(context, ilOp);
         }
 
-        private static void EmitBranch(ILEmitterCtx context, Cond cond)
+        private static void EmitBranch(ILEmitterCtx context, Condition cond)
         {
             OpCodeBImm64 op = (OpCodeBImm64)context.CurrOp;
 
diff --git a/ChocolArm64/Translation/ILEmitterCtx.cs b/ChocolArm64/Translation/ILEmitterCtx.cs
index 15e32644c3..a5ac84ea2f 100644
--- a/ChocolArm64/Translation/ILEmitterCtx.cs
+++ b/ChocolArm64/Translation/ILEmitterCtx.cs
@@ -108,7 +108,7 @@ namespace ChocolArm64.Translation
             //used by some unconditional instructions.
             ILLabel lblSkip = null;
 
-            if (CurrOp is OpCode32 op && op.Cond < Cond.Al)
+            if (CurrOp is OpCode32 op && op.Cond < Condition.Al)
             {
                 lblSkip = new ILLabel();
 
@@ -138,11 +138,11 @@ namespace ChocolArm64.Translation
             _ilBlock.Add(new ILBarrier());
         }
 
-        private Cond GetInverseCond(Cond cond)
+        private Condition GetInverseCond(Condition cond)
         {
             //Bit 0 of all conditions is basically a negation bit, so
             //inverting this bit has the effect of inverting the condition.
-            return (Cond)((int)cond ^ 1);
+            return (Condition)((int)cond ^ 1);
         }
 
         private void EmitSynchronization()
@@ -292,21 +292,21 @@ namespace ChocolArm64.Translation
             Stloc(CmpOptTmp1Index, IoType.Int);
         }
 
-        private Dictionary<Cond, OpCode> _branchOps = new Dictionary<Cond, OpCode>()
+        private Dictionary<Condition, OpCode> _branchOps = new Dictionary<Condition, OpCode>()
         {
-            { Cond.Eq,   OpCodes.Beq    },
-            { Cond.Ne,   OpCodes.Bne_Un },
-            { Cond.GeUn, OpCodes.Bge_Un },
-            { Cond.LtUn, OpCodes.Blt_Un },
-            { Cond.GtUn, OpCodes.Bgt_Un },
-            { Cond.LeUn, OpCodes.Ble_Un },
-            { Cond.Ge,   OpCodes.Bge    },
-            { Cond.Lt,   OpCodes.Blt    },
-            { Cond.Gt,   OpCodes.Bgt    },
-            { Cond.Le,   OpCodes.Ble    }
+            { Condition.Eq,   OpCodes.Beq    },
+            { Condition.Ne,   OpCodes.Bne_Un },
+            { Condition.GeUn, OpCodes.Bge_Un },
+            { Condition.LtUn, OpCodes.Blt_Un },
+            { Condition.GtUn, OpCodes.Bgt_Un },
+            { Condition.LeUn, OpCodes.Ble_Un },
+            { Condition.Ge,   OpCodes.Bge    },
+            { Condition.Lt,   OpCodes.Blt    },
+            { Condition.Gt,   OpCodes.Bgt    },
+            { Condition.Le,   OpCodes.Ble    }
         };
 
-        public void EmitCondBranch(ILLabel target, Cond cond)
+        public void EmitCondBranch(ILLabel target, Condition cond)
         {
             OpCode ilOp;