diff --git a/ARMeilleure/Instructions/InstEmitAluHelper.cs b/ARMeilleure/Instructions/InstEmitAluHelper.cs index 02131daa5e..64123d7dc2 100644 --- a/ARMeilleure/Instructions/InstEmitAluHelper.cs +++ b/ARMeilleure/Instructions/InstEmitAluHelper.cs @@ -222,30 +222,8 @@ namespace ARMeilleure.Instructions Operand zeroResult = m; Operand shiftResult = m; - Operand shiftSkip = Label(); - //Operand shiftZeroSkip = Label(); - setCarry &= op.SetFlags; - context.BranchIfTrue(shiftSkip, shiftIsZero); - - /* - // if zero, fudge the shift number a little - - switch (op.ShiftType) - { - case ShiftType.Lsr: zeroResult = GetLsrC(context, m, setCarry, 32); break; - case ShiftType.Asr: zeroResult = GetAsrC(context, m, setCarry, 32); break; - case ShiftType.Ror: - // ror 0 is rrx - zeroResult = GetRrxC(context, m, setCarry); - break; - } - - context.Branch(shiftSkip); - context.MarkLabel(shiftZeroSkip); - */ - switch (op.ShiftType) { case ShiftType.Lsl: shiftResult = EmitLslC(context, m, setCarry, s); break; @@ -254,8 +232,6 @@ namespace ARMeilleure.Instructions case ShiftType.Ror: shiftResult = EmitRorC(context, m, setCarry, s); break; } - context.MarkLabel(shiftSkip); - return context.ConditionalSelect(shiftIsZero, zeroResult, shiftResult); } @@ -361,16 +337,11 @@ namespace ARMeilleure.Instructions public static Operand EmitAsrC(ArmEmitterContext context, Operand m, bool setCarry, Operand shift) { - Operand normalShift = Label(); - Operand end = Label(); - Operand l32Result; Operand ge32Result; Operand less32 = context.ICompareLess(shift, Const(32)); - context.BranchIfTrue(normalShift, less32); - ge32Result = context.ShiftRightSI(m, Const(31)); if (setCarry) @@ -378,9 +349,6 @@ namespace ARMeilleure.Instructions SetCarryMLsb(context, ge32Result); } - context.Branch(end); - context.MarkLabel(normalShift); - l32Result = context.ShiftRightSI(m, shift); if (setCarry) { @@ -391,8 +359,6 @@ namespace ARMeilleure.Instructions SetFlag(context, PState.CFlag, cOut); } - context.MarkLabel(end); - return context.ConditionalSelect(less32, l32Result, ge32Result); } diff --git a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index 36e575f6ce..9ee4681409 100644 --- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -240,7 +240,7 @@ namespace ARMeilleure.Instructions public static void Vnmla_S(ArmEmitterContext context) { - if (false) //Optimizations.FastFP) + if (Optimizations.FastFP) { EmitScalarTernaryOpF32(context, (op1, op2, op3) => { @@ -258,11 +258,11 @@ namespace ARMeilleure.Instructions public static void Vnmls_S(ArmEmitterContext context) { - if (false)//Optimizations.FastFP) + if (Optimizations.FastFP) { EmitScalarTernaryOpF32(context, (op1, op2, op3) => { - return context.Subtract(op1, context.Multiply(op2, op3)); + return context.Add(context.Negate(op1), context.Multiply(op2, op3)); }); } else @@ -452,7 +452,7 @@ namespace ARMeilleure.Instructions public static void Vmla_V(ArmEmitterContext context) { - if (false)//Optimizations.FastFP) + if (Optimizations.FastFP) { EmitVectorTernaryOpF32(context, (op1, op2, op3) => context.Add(op1, context.Multiply(op2, op3))); } @@ -510,7 +510,7 @@ namespace ARMeilleure.Instructions public static void Vmls_V(ArmEmitterContext context) { - if (false)//Optimizations.FastFP) + if (Optimizations.FastFP) { EmitVectorTernaryOpF32(context, (op1, op2, op3) => context.Subtract(op1, context.Multiply(op2, op3))); } diff --git a/ARMeilleure/Translation/CompilerOptions.cs b/ARMeilleure/Translation/CompilerOptions.cs index 820bf7a2fc..53998ec6f3 100644 --- a/ARMeilleure/Translation/CompilerOptions.cs +++ b/ARMeilleure/Translation/CompilerOptions.cs @@ -11,6 +11,6 @@ namespace ARMeilleure.Translation Lsra = 1 << 2, MediumCq = SsaForm | Optimize, - HighCq = SsaForm | Optimize + HighCq = SsaForm | Optimize | Lsra } } \ No newline at end of file