From 145080aa26c248a53c042b1682ec32a9d85cd1d3 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 15 Sep 2018 15:47:19 +0200
Subject: [PATCH] Update CpuTestSimd.cs

---
 Ryujinx.Tests/Cpu/CpuTestSimd.cs | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index fe2c7bffa9..b423b4de73 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -113,11 +113,11 @@ namespace Ryujinx.Tests.Cpu
             for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
             {
                 ulong Grbg = TestContext.CurrentContext.Random.NextUInt();
-                ulong Val1 = GenNormal_S();
-                ulong Val2 = GenSubNormal_S();
+                ulong Rnd1 = GenNormal_S();
+                ulong Rnd2 = GenSubNormal_S();
 
-                yield return (Grbg << 32) | Val1;
-                yield return (Grbg << 32) | Val2;
+                yield return (Grbg << 32) | Rnd1;
+                yield return (Grbg << 32) | Rnd2;
             }
         }
 
@@ -154,11 +154,11 @@ namespace Ryujinx.Tests.Cpu
 
             for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
             {
-                ulong Val1 = GenNormal_S();
-                ulong Val2 = GenSubNormal_S();
+                ulong Rnd1 = GenNormal_S();
+                ulong Rnd2 = GenSubNormal_S();
 
-                yield return (Val1 << 32) | Val1;
-                yield return (Val2 << 32) | Val2;
+                yield return (Rnd1 << 32) | Rnd1;
+                yield return (Rnd2 << 32) | Rnd2;
             }
         }
 
@@ -195,11 +195,11 @@ namespace Ryujinx.Tests.Cpu
 
             for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
             {
-                ulong Val1 = GenNormal_D();
-                ulong Val2 = GenSubNormal_D();
+                ulong Rnd1 = GenNormal_D();
+                ulong Rnd2 = GenSubNormal_D();
 
-                yield return Val1;
-                yield return Val2;
+                yield return Rnd1;
+                yield return Rnd2;
             }
         }
 #endregion