Update CpuTestSimdCvt.cs
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1 changed files with 217 additions and 59 deletions
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@ -13,8 +13,24 @@ namespace Ryujinx.Tests.Cpu
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#if SimdCvt
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#region "ValueSource (Types)"
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private static IEnumerable<ulong> _1S_F_()
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private static IEnumerable<ulong> _1S_F_Cvt_()
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{
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// int
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yield return 0x00000000CF000001; // -2.1474839E9f (-2147483904)
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yield return 0x00000000CF000000; // -2.14748365E9f (-2147483648)
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yield return 0x00000000CEFFFFFF; // -2.14748352E9f (-2147483520)
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yield return 0x000000004F000001; // 2.1474839E9f (2147483904)
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yield return 0x000000004F000000; // 2.14748365E9f (2147483648)
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yield return 0x000000004EFFFFFF; // 2.14748352E9f (2147483520)
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// long
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yield return 0x00000000DF000001ul; // -9.223373E18f (-9223373136366403584)
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yield return 0x00000000DF000000ul; // -9.223372E18f (-9223372036854775808)
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yield return 0x00000000DEFFFFFFul; // -9.2233715E18f (-9223371487098961920)
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yield return 0x000000005F000001ul; // 9.223373E18f (9223373136366403584)
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yield return 0x000000005F000000ul; // 9.223372E18f (9223372036854775808)
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yield return 0x000000005EFFFFFFul; // 9.2233715E18f (9223371487098961920)
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max Subnormal
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@ -55,8 +71,24 @@ namespace Ryujinx.Tests.Cpu
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}
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}
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private static IEnumerable<ulong> _1D_F_()
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private static IEnumerable<ulong> _1D_F_Cvt_()
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{
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// int
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yield return 0xC1E0000000200000ul; // -2147483649.0000000d (-2147483649)
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yield return 0xC1E0000000000000ul; // -2147483648.0000000d (-2147483648)
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yield return 0xC1DFFFFFFFC00000ul; // -2147483647.0000000d (-2147483647)
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yield return 0x41E0000000200000ul; // 2147483649.0000000d (2147483649)
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yield return 0x41E0000000000000ul; // 2147483648.0000000d (2147483648)
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yield return 0x41DFFFFFFFC00000ul; // 2147483647.0000000d (2147483647)
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// long
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yield return 0xC3E0000000000001ul; // -9.2233720368547780E18d (-9223372036854778000)
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yield return 0xC3E0000000000000ul; // -9.2233720368547760E18d (-9223372036854776000)
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yield return 0xC3DFFFFFFFFFFFFFul; // -9.2233720368547750E18d (-9223372036854775000)
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yield return 0x43E0000000000001ul; // 9.2233720368547780E18d (9223372036854778000)
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yield return 0x43E0000000000000ul; // 9.2233720368547760E18d (9223372036854776000)
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yield return 0x43DFFFFFFFFFFFFFul; // 9.2233720368547750E18d (9223372036854775000)
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0x8010000000000000ul; // -Min Normal
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yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
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@ -110,7 +142,67 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _F_Cvt_Z_SU_S_SW_()
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private static uint[] _F_Cvt_AMPZ_SU_Gp_SW_()
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{
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return new uint[]
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{
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0x1E240000u, // FCVTAS W0, S0
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0x1E250000u, // FCVTAU W0, S0
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0x1E300000u, // FCVTMS W0, S0
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0x1E310000u, // FCVTMU W0, S0
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0x1E280000u, // FCVTPS W0, S0
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0x1E290000u, // FCVTPU W0, S0
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0x1E380000u, // FCVTZS W0, S0
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0x1E390000u // FCVTZU W0, S0
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};
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}
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private static uint[] _F_Cvt_AMPZ_SU_Gp_SX_()
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{
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return new uint[]
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{
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0x9E240000u, // FCVTAS X0, S0
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0x9E250000u, // FCVTAU X0, S0
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0x9E300000u, // FCVTMS X0, S0
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0x9E310000u, // FCVTMU X0, S0
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0x9E280000u, // FCVTPS X0, S0
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0x9E290000u, // FCVTPU X0, S0
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0x9E380000u, // FCVTZS X0, S0
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0x9E390000u // FCVTZU X0, S0
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};
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}
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private static uint[] _F_Cvt_AMPZ_SU_Gp_DW_()
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{
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return new uint[]
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{
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0x1E640000u, // FCVTAS W0, D0
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0x1E650000u, // FCVTAU W0, D0
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0x1E700000u, // FCVTMS W0, D0
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0x1E710000u, // FCVTMU W0, D0
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0x1E680000u, // FCVTPS W0, D0
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0x1E690000u, // FCVTPU W0, D0
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0x1E780000u, // FCVTZS W0, D0
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0x1E790000u // FCVTZU W0, D0
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};
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}
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private static uint[] _F_Cvt_AMPZ_SU_Gp_DX_()
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{
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return new uint[]
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{
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0x9E640000u, // FCVTAS X0, D0
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0x9E650000u, // FCVTAU X0, D0
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0x9E700000u, // FCVTMS X0, D0
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0x9E710000u, // FCVTMU X0, D0
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0x9E680000u, // FCVTPS X0, D0
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0x9E690000u, // FCVTPU X0, D0
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0x9E780000u, // FCVTZS X0, D0
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0x9E790000u // FCVTZU X0, D0
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};
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}
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private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SW_()
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{
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return new uint[]
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{
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@ -119,7 +211,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _F_Cvt_Z_SU_S_SX_()
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private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SX_()
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{
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return new uint[]
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{
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@ -128,7 +220,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _F_Cvt_Z_SU_S_DW_()
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private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DW_()
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{
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return new uint[]
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{
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@ -137,7 +229,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _F_Cvt_Z_SU_S_DX_()
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private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DX_()
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{
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return new uint[]
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{
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@ -146,7 +238,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _SU_Cvt_F_S_WS_()
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private static uint[] _SU_Cvt_F_Gp_Fixed_WS_()
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{
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return new uint[]
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{
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@ -155,7 +247,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _SU_Cvt_F_S_WD_()
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private static uint[] _SU_Cvt_F_Gp_Fixed_WD_()
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{
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return new uint[]
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{
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@ -164,7 +256,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _SU_Cvt_F_S_XS_()
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private static uint[] _SU_Cvt_F_Gp_Fixed_XS_()
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{
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return new uint[]
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{
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@ -173,7 +265,7 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _SU_Cvt_F_S_XD_()
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private static uint[] _SU_Cvt_F_Gp_Fixed_XD_()
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{
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return new uint[]
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{
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@ -184,20 +276,86 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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private const int RndCnt = 2;
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private const int RndCntFbits = 2;
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private const int RndCntFBits = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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[Test, Pairwise] [Explicit]
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public void F_Cvt_Z_SU_S_SW([ValueSource("_F_Cvt_Z_SU_S_SW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1S_F_")] ulong a,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFbits)] uint fbits)
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public void F_Cvt_AMPZ_SU_Gp_SW([ValueSource("_F_Cvt_AMPZ_SU_Gp_SW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1S_F_Cvt_")] ulong a)
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{
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uint scale = (64u - fbits) & 0x3Fu;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_AMPZ_SU_Gp_SX([ValueSource("_F_Cvt_AMPZ_SU_Gp_SX_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1S_F_Cvt_")] ulong a)
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{
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, x31: x31, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_AMPZ_SU_Gp_DW([ValueSource("_F_Cvt_AMPZ_SU_Gp_DW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1D_F_Cvt_")] ulong a)
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{
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_AMPZ_SU_Gp_DX([ValueSource("_F_Cvt_AMPZ_SU_Gp_DX_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1D_F_Cvt_")] ulong a)
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{
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> v1 = MakeVectorE0(a);
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SingleOpcode(opcodes, x31: x31, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_Z_SU_Gp_Fixed_SW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1S_F_Cvt_")] ulong a,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
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{
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uint scale = (64u - fBits) & 0x3Fu;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (scale << 10);
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@ -212,13 +370,13 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_Z_SU_S_SX([ValueSource("_F_Cvt_Z_SU_S_SX_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1S_F_")] ulong a,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntFbits)] uint fbits)
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public void F_Cvt_Z_SU_Gp_Fixed_SX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SX_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1S_F_Cvt_")] ulong a,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
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{
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uint scale = (64u - fbits) & 0x3Fu;
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uint scale = (64u - fBits) & 0x3Fu;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (scale << 10);
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@ -232,13 +390,13 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_Z_SU_S_DW([ValueSource("_F_Cvt_Z_SU_S_DW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1D_F_")] ulong a,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFbits)] uint fbits)
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public void F_Cvt_Z_SU_Gp_Fixed_DW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1D_F_Cvt_")] ulong a,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
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{
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uint scale = (64u - fbits) & 0x3Fu;
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uint scale = (64u - fBits) & 0x3Fu;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (scale << 10);
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@ -253,13 +411,13 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void F_Cvt_Z_SU_S_DX([ValueSource("_F_Cvt_Z_SU_S_DX_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1D_F_")] ulong a,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntFbits)] uint fbits)
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public void F_Cvt_Z_SU_Gp_Fixed_DX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DX_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(1u)] uint rn,
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[ValueSource("_1D_F_Cvt_")] ulong a,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
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{
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uint scale = (64u - fbits) & 0x3Fu;
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uint scale = (64u - fBits) & 0x3Fu;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (scale << 10);
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@ -273,13 +431,13 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_S_WS([ValueSource("_SU_Cvt_F_S_WS_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFbits)] uint fbits)
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public void SU_Cvt_F_Gp_Fixed_WS([ValueSource("_SU_Cvt_F_Gp_Fixed_WS_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
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{
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uint scale = (64u - fbits) & 0x3Fu;
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uint scale = (64u - fBits) & 0x3Fu;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (scale << 10);
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@ -294,13 +452,13 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_S_WD([ValueSource("_SU_Cvt_F_S_WD_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFbits)] uint fbits)
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public void SU_Cvt_F_Gp_Fixed_WD([ValueSource("_SU_Cvt_F_Gp_Fixed_WD_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[ValueSource("_W_")] [Random(RndCnt)] uint wn,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
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{
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uint scale = (64u - fbits) & 0x3Fu;
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uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (scale << 10);
|
||||
|
|
@ -315,13 +473,13 @@ namespace Ryujinx.Tests.Cpu
|
|||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_S_XS([ValueSource("_SU_Cvt_F_S_XS_")] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFbits)] uint fbits)
|
||||
public void SU_Cvt_F_Gp_Fixed_XS([ValueSource("_SU_Cvt_F_Gp_Fixed_XS_")] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fbits) & 0x3Fu;
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (scale << 10);
|
||||
|
|
@ -336,13 +494,13 @@ namespace Ryujinx.Tests.Cpu
|
|||
}
|
||||
|
||||
[Test, Pairwise] [Explicit]
|
||||
public void SU_Cvt_F_S_XD([ValueSource("_SU_Cvt_F_S_XD_")] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFbits)] uint fbits)
|
||||
public void SU_Cvt_F_Gp_Fixed_XD([ValueSource("_SU_Cvt_F_Gp_Fixed_XD_")] uint opcodes,
|
||||
[Values(0u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
|
||||
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
|
||||
{
|
||||
uint scale = (64u - fbits) & 0x3Fu;
|
||||
uint scale = (64u - fBits) & 0x3Fu;
|
||||
|
||||
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcodes |= (scale << 10);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue