Update CpuTestSimd.cs
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1 changed files with 159 additions and 113 deletions
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@ -4,6 +4,8 @@ using ChocolArm64.State;
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using NUnit.Framework;
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using System;
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using System.Collections.Generic;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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@ -78,76 +80,144 @@ namespace Ryujinx.Tests.Cpu
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1S_F_()
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private static IEnumerable<ulong> _1S_F_()
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{
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return new ulong[]
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yield return 0x00000000FF7FFFFFul; // -Max Normal, float.MinValue
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max SubNormal
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yield return 0x0000000080000001ul; // -Min SubNormal
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yield return 0x0000000000000001ul; // +Min SubNormal
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yield return 0x00000000007FFFFFul; // +Max SubNormal
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x000000007F7FFFFFul; // +Max Normal, float.MaxValue
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if (!NoZeros)
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{
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0x00000000FFFFFFFFul, // -QNaN (all ones payload)
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0x00000000FFBFFFFFul, // -SNaN (all ones payload)
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0x00000000FF800000ul, // -INF
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0x00000000FF7FFFFFul, // -Max Normal, float.MinValue
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0x0000000080800000ul, // -Min Normal
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0x00000000807FFFFFul, // -Max SubNormal
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0x0000000080000001ul, // -Min SubNormal
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0x0000000080000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000000000001ul, // +Min SubNormal
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0x00000000007FFFFFul, // +Max SubNormal
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0x0000000000800000ul, // +Min Normal
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0x000000007F7FFFFFul, // +Max Normal, float.MaxValue
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0x000000007F800000ul, // +INF
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0x000000007FBFFFFFul, // +SNaN (all ones payload)
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0x000000007FFFFFFFul // +QNaN (all ones payload)
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};
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yield return 0x0000000080000000ul; // -0
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yield return 0x0000000000000000ul; // +0
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}
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if (!NoInfs)
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{
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yield return 0x00000000FF800000ul; // -INF
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yield return 0x000000007F800000ul; // +INF
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}
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if (!NoNaNs)
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{
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yield return 0x00000000FFFFFFFFul; // -QNaN (all ones payload)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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yield return 0x000000007FFFFFFFul; // +QNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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float Rnd;
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do Rnd = TestContext.CurrentContext.Random.NextFloat(float.MinValue, float.MaxValue);
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while (Rnd == 0f); // -0, +0
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ulong Noise = TestContext.CurrentContext.Random.NextUInt();
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ulong Value = (uint)BitConverter.SingleToInt32Bits(Rnd);
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yield return (Noise << 32) | Value;
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}
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}
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private static ulong[] _2S_F_()
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private static IEnumerable<ulong> _2S_F_()
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{
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return new ulong[]
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yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal, float.MinValue
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yield return 0x8080000080800000ul; // -Min Normal
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yield return 0x807FFFFF807FFFFFul; // -Max SubNormal
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yield return 0x8000000180000001ul; // -Min SubNormal
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yield return 0x0000000100000001ul; // +Min SubNormal
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yield return 0x007FFFFF007FFFFFul; // +Max SubNormal
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yield return 0x0080000000800000ul; // +Min Normal
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yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal, float.MaxValue
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if (!NoZeros)
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{
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0xFFFFFFFFFFFFFFFFul, // -QNaN (all ones payload)
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0xFFBFFFFFFFBFFFFFul, // -SNaN (all ones payload)
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0xFF800000FF800000ul, // -INF
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0xFF7FFFFFFF7FFFFFul, // -Max Normal, float.MinValue
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0x8080000080800000ul, // -Min Normal
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0x807FFFFF807FFFFFul, // -Max SubNormal
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0x8000000180000001ul, // -Min SubNormal
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0x8000000080000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000100000001ul, // +Min SubNormal
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0x007FFFFF007FFFFFul, // +Max SubNormal
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0x0080000000800000ul, // +Min Normal
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0x7F7FFFFF7F7FFFFFul, // +Max Normal, float.MaxValue
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0x7F8000007F800000ul, // +INF
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0x7FBFFFFF7FBFFFFFul, // +SNaN (all ones payload)
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0x7FFFFFFF7FFFFFFFul // +QNaN (all ones payload)
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};
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yield return 0x8000000080000000ul; // -0
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yield return 0x0000000000000000ul; // +0
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}
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if (!NoInfs)
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{
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yield return 0xFF800000FF800000ul; // -INF
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yield return 0x7F8000007F800000ul; // +INF
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}
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if (!NoNaNs)
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{
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yield return 0xFFFFFFFFFFFFFFFFul; // -QNaN (all ones payload)
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yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
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yield return 0x7FFFFFFF7FFFFFFFul; // +QNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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float Rnd;
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do Rnd = TestContext.CurrentContext.Random.NextFloat(float.MinValue, float.MaxValue);
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while (Rnd == 0f); // -0, +0
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ulong Value = (uint)BitConverter.SingleToInt32Bits(Rnd);
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yield return (Value << 32) | Value;
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}
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}
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private static ulong[] _1D_F_()
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private static IEnumerable<ulong> _1D_F_()
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{
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return new ulong[]
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal, double.MinValue
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yield return 0x8010000000000000ul; // -Min Normal
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yield return 0x800FFFFFFFFFFFFFul; // -Max SubNormal
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yield return 0x8000000000000001ul; // -Min SubNormal
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yield return 0x0000000000000001ul; // +Min SubNormal
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yield return 0x000FFFFFFFFFFFFFul; // +Max SubNormal
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yield return 0x0010000000000000ul; // +Min Normal
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yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal, double.MaxValue
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if (!NoZeros)
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{
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0xFFFFFFFFFFFFFFFFul, // -QNaN (all ones payload)
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0xFFF7FFFFFFFFFFFFul, // -SNaN (all ones payload)
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0xFFF0000000000000ul, // -INF
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0xFFEFFFFFFFFFFFFFul, // -Max Normal, double.MinValue
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0x8010000000000000ul, // -Min Normal
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0x800FFFFFFFFFFFFFul, // -Max SubNormal
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0x8000000000000001ul, // -Min SubNormal
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0x8000000000000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000000000001ul, // +Min SubNormal
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0x000FFFFFFFFFFFFFul, // +Max SubNormal
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0x0010000000000000ul, // +Min Normal
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0x7FEFFFFFFFFFFFFFul, // +Max Normal, double.MaxValue
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0x7FF0000000000000ul, // +INF
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0x7FF7FFFFFFFFFFFFul, // +SNaN (all ones payload)
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0x7FFFFFFFFFFFFFFFul // +QNaN (all ones payload)
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};
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yield return 0x8000000000000000ul; // -0
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yield return 0x0000000000000000ul; // +0
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}
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if (!NoInfs)
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{
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yield return 0xFFF0000000000000ul; // -INF
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yield return 0x7FF0000000000000ul; // +INF
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}
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if (!NoNaNs)
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{
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yield return 0xFFFFFFFFFFFFFFFFul; // -QNaN (all ones payload)
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yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
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yield return 0x7FFFFFFFFFFFFFFFul; // +QNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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double Rnd;
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do Rnd = TestContext.CurrentContext.Random.NextDouble(double.MinValue, double.MaxValue);
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while (Rnd == 0d); // -0, +0
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ulong Value = (ulong)BitConverter.DoubleToInt64Bits(Rnd);
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yield return Value;
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}
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}
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#endregion
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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private const int RndCnt = 2;
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[Test, Pairwise, Description("ABS <V><d>, <V><n>")]
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@ -648,19 +718,19 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1S_F_")] [Random(RndCnt)] ulong A)
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[ValueSource("_1S_F_")] ulong Z,
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[ValueSource("_1S_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x5E21A800; // FCVTNS S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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@ -669,84 +739,72 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x5E61A800; // FCVTNS D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_2S_F_")] [Random(RndCnt)] ulong A,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x0E21A800; // FCVTNS V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x4E61A800; // FCVTNS V0.2D, V0.2D
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
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public void Fcvtnu_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1S_F_")] [Random(RndCnt)] ulong A)
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[ValueSource("_1S_F_")] ulong Z,
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[ValueSource("_1S_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x7E21A800; // FCVTNU S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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@ -755,66 +813,54 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
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public void Fcvtnu_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x7E61A800; // FCVTNU D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtnu_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_2S_F_")] [Random(RndCnt)] ulong A,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x2E21A800; // FCVTNU V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtnu_V_2D([Values(0u)] uint Rd,
|
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[Values(1u, 0u)] uint Rn,
|
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
|
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
|
||||
[ValueSource("_1D_F_")] ulong Z,
|
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[ValueSource("_1D_F_")] ulong A)
|
||||
{
|
||||
//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
|
||||
|
||||
uint Opcode = 0x6E61A800; // FCVTNU V0.2D, V0.2D
|
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("NEG <V><d>, <V><n>")]
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue