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Update AInstEmitSimdArithmetic.cs

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LDj3SNuD 2018-07-14 21:04:43 +02:00 • committed by GitHub
commit 157965b9de
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1 changed files with 11 additions and 1 deletions
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12
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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@ -163,12 +163,19 @@ namespace ChocolArm64.Instruction
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Elems = 8 >> Op.Size; int Elems = 8 >> Op.Size;
int ESize = 8 << Op.Size; int ESize = 8 << Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0; int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
long RoundConst = 1L << (ESize - 1); long RoundConst = 1L << (ESize - 1);
if (Part != 0)
{
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
}
for (int Index = 0; Index < Elems; Index++) for (int Index = 0; Index < Elems; Index++)
{ {
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1); EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
@ -185,9 +192,12 @@ namespace ChocolArm64.Instruction
Context.EmitLsr(ESize); Context.EmitLsr(ESize);
EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size); EmitVectorInsertTmp(Context, Part + Index, Op.Size);
} }
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Part == 0) if (Part == 0)
{ {
EmitVectorZeroUpper(Context, Op.Rd); EmitVectorZeroUpper(Context, Op.Rd);