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Update Instructions.cs

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LDj3SNuD 2018-08-29 00:14:09 +02:00 • committed by GitHub
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204
Ryujinx.Tests/Cpu/Tester/Instructions.cs
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@ -5270,6 +5270,57 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// saddl_advsimd.html
public static void Saddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool o1 = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
BigInteger sum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
if (sub_op)
{
sum = element1 - element2;
}
else
{
sum = element1 + element2;
}
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
}
V(d, result);
}
// saddw_advsimd.html
public static void Saddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
@ -6029,6 +6080,57 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// ssubl_advsimd.html
public static void Ssubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool o1 = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
BigInteger sum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
if (sub_op)
{
sum = element1 - element2;
}
else
{
sum = element1 + element2;
}
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
}
V(d, result);
}
// ssubw_advsimd.html
public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
@ -6470,6 +6572,57 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// uaddl_advsimd.html
public static void Uaddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool o1 = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
BigInteger sum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
if (sub_op)
{
sum = element1 - element2;
}
else
{
sum = element1 + element2;
}
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
}
V(d, result);
}
// uaddw_advsimd.html
public static void Uaddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
@ -6947,6 +7100,57 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// usubl_advsimd.html
public static void Usubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool o1 = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
BigInteger element1;
BigInteger element2;
BigInteger sum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
if (sub_op)
{
sum = element1 - element2;
}
else
{
sum = element1 + element2;
}
Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0));
}
V(d, result);
}
// usubw_advsimd.html
public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{