From 19994b47801cd7af023560f27e3eea9f8e82874b Mon Sep 17 00:00:00 2001
From: unknown <mgnjulien@gmail.com>
Date: Sun, 25 Feb 2018 18:44:27 +0100
Subject: [PATCH] add frintx_S test

---
 Ryujinx.Tests/Cpu/CpuTest.cs               |  7 ++--
 Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 44 ++++++++++++++++++++++
 2 files changed, 48 insertions(+), 3 deletions(-)
 create mode 100644 Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs

diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs
index 7af2d55d0a..f9599da2ad 100644
--- a/Ryujinx.Tests/Cpu/CpuTest.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest.cs
@@ -59,7 +59,7 @@ namespace Ryujinx.Tests.Cpu
 
         protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0,
                                       AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec),
-                                      bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false)
+                                      bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false, int Fpcr = 0x0)
         {
             Thread.ThreadState.X0 = X0;
             Thread.ThreadState.X1 = X1;
@@ -72,6 +72,7 @@ namespace Ryujinx.Tests.Cpu
             Thread.ThreadState.Carry = Carry;
             Thread.ThreadState.Zero = Zero;
             Thread.ThreadState.Negative = Negative;
+            Thread.ThreadState.Fpcr = Fpcr;
         }
 
         protected void ExecuteOpcodes()
@@ -94,12 +95,12 @@ namespace Ryujinx.Tests.Cpu
         protected AThreadState SingleOpcode(uint Opcode,
                                             ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0,
                                             AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec),
-                                            bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false)
+                                            bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false, int Fpcr = 0x0)
         {
             this.Opcode(Opcode);
             this.Opcode(0xD4200000); // BRK #0
             this.Opcode(0xD65F03C0); // RET
-            SetThreadState(X0, X1, X2, X31, V0, V1, V2, Overflow, Carry, Zero, Negative);
+            SetThreadState(X0, X1, X2, X31, V0, V1, V2, Overflow, Carry, Zero, Negative, Fpcr);
             ExecuteOpcodes();
 
             return GetThreadState();
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
new file mode 100644
index 0000000000..ab5337ba82
--- /dev/null
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
@@ -0,0 +1,44 @@
+using ChocolArm64.State;
+using NUnit.Framework;
+
+namespace Ryujinx.Tests.Cpu
+{
+    public class CpuTestSimdArithmetic : CpuTest
+    {
+    	[TestCase(0x3FE66666u, 'N', 0x40000000u)]
+    	[TestCase(0x3F99999Au, 'N', 0x3F800000u)]
+    	[TestCase(0x404CCCCDu, 'P', 0x40800000u)]
+    	[TestCase(0x40733333u, 'P', 0x40800000u)]
+    	[TestCase(0x404CCCCDu, 'M', 0x40400000u)]
+    	[TestCase(0x40733333u, 'M', 0x40400000u)]
+    	[TestCase(0x3F99999Au, 'Z', 0x3F800000u)]
+    	[TestCase(0x3FE66666u, 'Z', 0x3F800000u)]
+    	public void Frintx_S(uint A, char RoundType, uint Result)
+        {
+        	int FpcrTemp = 0x0;
+        	switch(RoundType)
+        	{
+        		case 'N':
+        		FpcrTemp &= ~((1 << 23) | (1 << 22));
+        		break;
+
+        		case 'P':
+        		FpcrTemp &= ~(1 << 23);
+        		FpcrTemp |= 1 << 22;
+        		break;
+
+        		case 'M':
+        		FpcrTemp |= 1 << 23;
+        		FpcrTemp &= ~(1 << 22);
+        		break;
+
+        		case 'Z':
+        		FpcrTemp |= (1 << 23) | (1 << 22);
+        		break;
+        	}
+        	AVec V1 = new AVec { X0 = A };
+        	AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp);
+        	Assert.AreEqual(Result, ThreadState.V0.X0);
+        }
+    }
+}
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