Update CpuTestSimd.cs
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1 changed files with 173 additions and 1 deletions
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@ -11,7 +11,7 @@ namespace Ryujinx.Tests.Cpu
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using Tester;
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using Tester.Types;
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[Category("Simd")/*, Ignore("Tested: first half of 2018.")*/]
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[Category("Simd")/*, Ignore("Tested: second half of 2018.")*/]
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public sealed class CpuTestSimd : CpuTest
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{
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#if Simd
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@ -775,6 +775,178 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
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public void Rbit_V_8B([ValueSource("_8B_")] [Random(1)] ulong A)
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{
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uint Opcode = 0x2E605820; // RBIT V0.8B, V1.8B
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
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public void Rbit_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1)
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{
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uint Opcode = 0x6E605820; // RBIT V0.16B, V1.16B
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
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public void Rev16_V_8B([ValueSource("_8B_")] [Random(1)] ulong A)
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{
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uint Opcode = 0x0E201820; // REV16 V0.8B, V1.8B
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
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public void Rev16_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1)
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{
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uint Opcode = 0x4E201820; // REV16 V0.16B, V1.16B
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
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public void Rev32_V_8B_4H([ValueSource("_8B4H_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u)] uint size) // <8B, 4H>
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{
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uint Opcode = 0x2E200820; // REV32 V0.8B, V1.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
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public void Rev32_V_16B_8H([ValueSource("_8B4H_")] [Random(1)] ulong A0,
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[ValueSource("_8B4H_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u)] uint size) // <16B, 8H>
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{
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uint Opcode = 0x6E200820; // REV32 V0.16B, V1.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
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public void Rev64_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E200820; // REV64 V0.8B, V1.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
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public void Rev64_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
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[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
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{
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uint Opcode = 0x4E200820; // REV64 V0.16B, V1.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("SQXTN <Vb><d>, <Va><n>")]
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public void Sqxtn_S_HB_SH_DS([ValueSource("_1H1S1D_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
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