From 29add160ae54d703b213ee423cd6fdb7e4f1650a Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 13 Oct 2018 01:12:01 +0200
Subject: [PATCH] Update CpuTestSimdIns.cs

---
 Ryujinx.Tests/Cpu/CpuTestSimdIns.cs | 109 +++++++++++++++++++++++++++-
 1 file changed, 108 insertions(+), 1 deletion(-)

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs b/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
index 387cdf5dd9..0b227edbb6 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
@@ -14,6 +14,27 @@ namespace Ryujinx.Tests.Cpu
 #if SimdIns
 
 #region "ValueSource"
+        private static ulong[] _1D_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+                                 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+        }
+
+        private static ulong[] _8B4H_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+        }
+
+        private static ulong[] _8B4H2S_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+        }
+
         private static uint[] _W_()
         {
             return new uint[] { 0x00000000u, 0x0000007Fu,
@@ -39,7 +60,7 @@ namespace Ryujinx.Tests.Cpu
                              [Values(0, 1, 2)] int Size,  // Q0: <8B,  4H, 2S>
                              [Values(0b0u, 0b1u)] uint Q) // Q1: <16B, 8H, 4S>
         {
-            uint Imm5 = (1U << Size) & 0x1F;
+            uint Imm5 = (1u << Size) & 0x1Fu;
 
             uint Opcode = 0x0E000C00; // RESERVED
             Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -69,6 +90,92 @@ namespace Ryujinx.Tests.Cpu
 
             CompareAgainstUnicorn();
         }
+
+        [Test, Pairwise, Description("SMOV <Wd>, <Vn>.<Ts>[<index>]")]
+        public void Smov_S_W([Values(0u, 31u)] uint Rd,
+                             [Values(1u)]      uint Rn,
+                             [ValueSource("_8B4H_")] [Random(RndCnt)] ulong A,
+                             [Values(0, 1)] int Size, // <B, H>
+                             [Values(0u, 1u, 2u, 3u)] uint Index)
+        {
+            uint Imm5 = (Index << (Size + 1) | 1u << Size) & 0x1Fu;
+
+            uint Opcode = 0x0E002C00; // RESERVED
+            Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= (Imm5 << 16);
+
+            ulong _X0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
+            uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcode, X0: _X0, X31: _W31, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("SMOV <Xd>, <Vn>.<Ts>[<index>]")]
+        public void Smov_S_X([Values(0u, 31u)] uint Rd,
+                             [Values(1u)]      uint Rn,
+                             [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                             [Values(0, 1, 2)] int Size, // <B, H, S>
+                             [Values(0u, 1u)] uint Index)
+        {
+            uint Imm5 = (Index << (Size + 1) | 1u << Size) & 0x1Fu;
+
+            uint Opcode = 0x4E002C00; // RESERVED
+            Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= (Imm5 << 16);
+
+            ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("UMOV <Wd>, <Vn>.<Ts>[<index>]")]
+        public void Umov_S_W([Values(0u, 31u)] uint Rd,
+                             [Values(1u)]      uint Rn,
+                             [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                             [Values(0, 1, 2)] int Size, // <B, H, S>
+                             [Values(0u, 1u)] uint Index)
+        {
+            uint Imm5 = (Index << (Size + 1) | 1u << Size) & 0x1Fu;
+
+            uint Opcode = 0x0E003C00; // RESERVED
+            Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= (Imm5 << 16);
+
+            ulong _X0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
+            uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcode, X0: _X0, X31: _W31, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("UMOV <Xd>, <Vn>.<Ts>[<index>]")]
+        public void Umov_S_X([Values(0u, 31u)] uint Rd,
+                             [Values(1u)]      uint Rn,
+                             [ValueSource("_1D_")] [Random(RndCnt)] ulong A,
+                             [Values(3)] int Size, // <D>
+                             [Values(0u)] uint Index)
+        {
+            uint Imm5 = (Index << (Size + 1) | 1u << Size) & 0x1Fu;
+
+            uint Opcode = 0x4E003C00; // RESERVED
+            Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= (Imm5 << 16);
+
+            ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
 #endif
     }
 }