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Update AInstEmitSimdArithmetic.cs

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LDj3SNuD 2018-07-30 02:32:15 +02:00 • committed by GitHub
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ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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@ -1052,6 +1052,46 @@ namespace ChocolArm64.Instruction
EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Mul)); EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Mul));
} }
public static void Sqabs_S(AILEmitterCtx Context)
{
EmitScalarSaturatingUnaryOpSx(Context, () => EmitAbs(Context));
}
public static void Sqabs_V(AILEmitterCtx Context)
{
EmitVectorSaturatingUnaryOpSx(Context, () => EmitAbs(Context));
}
public static void Sqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
}
public static void Sqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
}
public static void Sqneg_S(AILEmitterCtx Context)
{
EmitScalarSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
}
public static void Sqneg_V(AILEmitterCtx Context)
{
EmitVectorSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
}
public static void Sqsub_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
}
public static void Sqsub_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
}
public static void Sqxtn_S(AILEmitterCtx Context) public static void Sqxtn_S(AILEmitterCtx Context)
{ {
EmitScalarSaturatingNarrowOpSxSx(Context, () => { }); EmitScalarSaturatingNarrowOpSxSx(Context, () => { });
@ -1099,6 +1139,16 @@ namespace ChocolArm64.Instruction
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: false); EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: false);
} }
public static void Suqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Accumulate);
}
public static void Suqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Accumulate);
}
public static void Uaba_V(AILEmitterCtx Context) public static void Uaba_V(AILEmitterCtx Context)
{ {
EmitVectorTernaryOpZx(Context, () => EmitVectorTernaryOpZx(Context, () =>
@ -1221,6 +1271,26 @@ namespace ChocolArm64.Instruction
EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul)); EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
} }
public static void Uqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Add);
}
public static void Uqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Add);
}
public static void Uqsub_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Sub);
}
public static void Uqsub_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Sub);
}
public static void Uqxtn_S(AILEmitterCtx Context) public static void Uqxtn_S(AILEmitterCtx Context)
{ {
EmitScalarSaturatingNarrowOpZxZx(Context, () => { }); EmitScalarSaturatingNarrowOpZxZx(Context, () => { });
@ -1231,6 +1301,16 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingNarrowOpZxZx(Context, () => { }); EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
} }
public static void Usqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
}
public static void Usqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
}
public static void Usubw_V(AILEmitterCtx Context) public static void Usubw_V(AILEmitterCtx Context)
{ {
EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub)); EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));