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Update InstEmitSimdArithmetic.cs

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LDj3SNuD 2018-11-29 03:05:36 +01:00 • committed by GitHub
commit 33b4af6a59
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1 changed files with 28 additions and 1 deletions
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27
ChocolArm64/Instructions/InstEmitSimdArithmetic.cs
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@ -1637,9 +1637,36 @@ namespace ChocolArm64.Instructions
} }
public static void Neg_V(ILEmitterCtx context) public static void Neg_V(ILEmitterCtx context)
{
if (Optimizations.UseSse2)
{
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
Type[] typesSub = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] };
string[] namesSzv = new string[] { nameof(VectorHelper.VectorSByteZero),
nameof(VectorHelper.VectorInt16Zero),
nameof(VectorHelper.VectorInt32Zero),
nameof(VectorHelper.VectorInt64Zero) };
VectorHelper.EmitCall(context, namesSzv[op.Size]);
EmitLdvecWithSignedCast(context, op.Rn, op.Size);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSub));
EmitStvecWithSignedCast(context, op.Rd, op.Size);
if (op.RegisterSize == RegisterSize.Simd64)
{
EmitVectorZeroUpper(context, op.Rd);
}
}
else
{ {
EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg));
} }
}
public static void Raddhn_V(ILEmitterCtx context) public static void Raddhn_V(ILEmitterCtx context)
{ {