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Fix regression on Sha1h and revert Fcm** changes

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This commit is contained in:
gdkchan 2019-07-23 21:34:09 -03:00
commit 3a0676c596
3 changed files with 17 additions and 15 deletions
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2
ARMeilleure/CodeGen/X86/CodeGenerator.cs
View file

@ -625,6 +625,8 @@ namespace ARMeilleure.CodeGen.X86
Operand dest = operation.Dest; Operand dest = operation.Dest;
Operand source = operation.GetSource(0); Operand source = operation.GetSource(0);
EnsureSameType(dest, source);
Debug.Assert(dest.Type.IsInteger() || source.Kind != OperandKind.Constant); Debug.Assert(dest.Type.IsInteger() || source.Kind != OperandKind.Constant);
//Moves to the same register are useless. //Moves to the same register are useless.

26
ARMeilleure/Instructions/InstEmitSimdCmp.cs
View file

@ -324,7 +324,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThan, scalar: true, reverseOps: true); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThanOrEqual, scalar: true);
} }
else else
{ {
@ -336,7 +336,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThan, scalar: false, reverseOps: true); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThanOrEqual, scalar: false);
} }
else else
{ {
@ -348,7 +348,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThanOrEqual, scalar: true, reverseOps: true); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThan, scalar: true);
} }
else else
{ {
@ -360,7 +360,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThanOrEqual, scalar: false, reverseOps: true); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThan, scalar: false);
} }
else else
{ {
@ -372,7 +372,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThanOrEqual, scalar: true); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThanOrEqual, scalar: true, isLeOrLt: true);
} }
else else
{ {
@ -384,7 +384,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThanOrEqual, scalar: false); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThanOrEqual, scalar: false, isLeOrLt: true);
} }
else else
{ {
@ -396,7 +396,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThan, scalar: true); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThan, scalar: true, isLeOrLt: true);
} }
else else
{ {
@ -408,7 +408,7 @@ namespace ARMeilleure.Instructions
{ {
if (Optimizations.FastFP && Optimizations.UseSse2) if (Optimizations.FastFP && Optimizations.UseSse2)
{ {
EmitCmpSseOrSse2OpF(context, CmpCondition.LessThan, scalar: false); EmitCmpSseOrSse2OpF(context, CmpCondition.GreaterThan, scalar: false, isLeOrLt: true);
} }
else else
{ {
@ -656,15 +656,15 @@ namespace ARMeilleure.Instructions
private enum CmpCondition private enum CmpCondition
{ {
Equal = 0, Equal = 0,
LessThan = 1, GreaterThanOrEqual = 5,
LessThanOrEqual = 2 GreaterThan = 6
} }
private static void EmitCmpSseOrSse2OpF( private static void EmitCmpSseOrSse2OpF(
ArmEmitterContext context, ArmEmitterContext context,
CmpCondition cond, CmpCondition cond,
bool scalar, bool scalar,
bool reverseOps = false) bool isLeOrLt = false)
{ {
OpCodeSimd op = (OpCodeSimd)context.CurrOp; OpCodeSimd op = (OpCodeSimd)context.CurrOp;
@ -677,7 +677,7 @@ namespace ARMeilleure.Instructions
{ {
Intrinsic inst = scalar ? Intrinsic.X86Cmpss : Intrinsic.X86Cmpps; Intrinsic inst = scalar ? Intrinsic.X86Cmpss : Intrinsic.X86Cmpps;
Operand res = reverseOps Operand res = isLeOrLt
? context.AddIntrinsic(inst, m, n, Const((int)cond)) ? context.AddIntrinsic(inst, m, n, Const((int)cond))
: context.AddIntrinsic(inst, n, m, Const((int)cond)); : context.AddIntrinsic(inst, n, m, Const((int)cond));
@ -696,7 +696,7 @@ namespace ARMeilleure.Instructions
{ {
Intrinsic inst = scalar ? Intrinsic.X86Cmpsd : Intrinsic.X86Cmppd; Intrinsic inst = scalar ? Intrinsic.X86Cmpsd : Intrinsic.X86Cmppd;
Operand res = reverseOps Operand res = isLeOrLt
? context.AddIntrinsic(inst, m, n, Const((int)cond)) ? context.AddIntrinsic(inst, m, n, Const((int)cond))
: context.AddIntrinsic(inst, n, m, Const((int)cond)); : context.AddIntrinsic(inst, n, m, Const((int)cond));

2
ARMeilleure/Instructions/InstEmitSimdHash.cs
View file

@ -32,7 +32,7 @@ namespace ARMeilleure.Instructions
Operand res = context.Call(new _U32_U32(SoftFallback.FixedRotate), ne); Operand res = context.Call(new _U32_U32(SoftFallback.FixedRotate), ne);
context.Copy(GetVec(op.Rd), res); context.Copy(GetVec(op.Rd), context.VectorCreateScalar(res));
} }
public static void Sha1m_V(ArmEmitterContext context) public static void Sha1m_V(ArmEmitterContext context)