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Update CpuTestSimdMove.cs

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LDj3SNuD 2018-04-12 02:27:47 +02:00 • committed by GitHub
parent 00eaff9468
commit 3b647cdeb0
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Ryujinx.Tests/Cpu/CpuTestSimdMove.cs
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@ -5,6 +5,38 @@ namespace Ryujinx.Tests.Cpu
{
public class CpuTestSimdMove : CpuTest
{
[Test, Description("trn1 v0.4s, v1.4s, v2.4s")]
public void Trn1_V([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3,
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
{
uint Opcode = 0x4E822820;
AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 };
AVec V2 = new AVec { W0 = B0, W1 = B1, W2 = B2, W3 = B3 };
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.That(ThreadState.V0.W0, Is.EqualTo(A0));
Assert.That(ThreadState.V0.W1, Is.EqualTo(B0));
Assert.That(ThreadState.V0.W2, Is.EqualTo(A2));
Assert.That(ThreadState.V0.W3, Is.EqualTo(B2));
}
[Test, Description("trn2 v0.4s, v1.4s, v2.4s")]
public void Trn2_V([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3,
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
{
uint Opcode = 0x4E826820;
AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 };
AVec V2 = new AVec { W0 = B0, W1 = B1, W2 = B2, W3 = B3 };
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.That(ThreadState.V0.W0, Is.EqualTo(A1));
Assert.That(ThreadState.V0.W1, Is.EqualTo(B1));
Assert.That(ThreadState.V0.W2, Is.EqualTo(A3));
Assert.That(ThreadState.V0.W3, Is.EqualTo(B3));
}
[TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]
[TestCase(1u, 0u, 0x2313221221112010ul, 0x2717261625152414ul)]
[TestCase(0u, 1u, 0x2322131221201110ul, 0x0000000000000000ul)]