Update AInstEmitSimdShift.cs
This commit is contained in:
parent
bbd393852b
commit
4127bcf011
1 changed files with 137 additions and 92 deletions
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@ -14,20 +14,24 @@ namespace ChocolArm64.Instruction
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size);
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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Context.Emit(OpCodes.Shl);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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}
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}
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public static void Shl_V(AILEmitterCtx Context)
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public static void Shl_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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EmitVectorUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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}
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}
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public static void Shll_V(AILEmitterCtx Context)
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public static void Shll_V(AILEmitterCtx Context)
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@ -103,15 +107,26 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
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EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
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}
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}
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public static void Srshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round);
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}
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public static void Srshr_V(AILEmitterCtx Context)
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public static void Srshr_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round);
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}
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int Shift = GetImmShr(Op);
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public static void Srsra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context,
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ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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long RoundConst = 1L << (Shift - 1);
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public static void Srsra_V(AILEmitterCtx Context)
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{
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EmitVectorRoundShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift, RoundConst);
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EmitVectorShrImmOpSx(Context,
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ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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}
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public static void Sshl_V(AILEmitterCtx Context)
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public static void Sshl_V(AILEmitterCtx Context)
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@ -128,35 +143,44 @@ namespace ChocolArm64.Instruction
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public static void Sshr_S(AILEmitterCtx Context)
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public static void Sshr_S(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx);
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EmitVectorExtractSx(Context, Op.Rn, 0, Op.Size);
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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}
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}
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public static void Sshr_V(AILEmitterCtx Context)
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public static void Sshr_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitShrImmOp(Context, ShrImmFlags.VectorSx);
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}
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EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), GetImmShr(Op));
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public static void Ssra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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}
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public static void Ssra_V(AILEmitterCtx Context)
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public static void Ssra_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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Action Emit = () =>
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public static void Urshr_S(AILEmitterCtx Context)
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{
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{
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Context.Emit(OpCodes.Shr);
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round);
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Context.Emit(OpCodes.Add);
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}
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};
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EmitVectorShImmTernarySx(Context, Emit, GetImmShr(Op));
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public static void Urshr_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round);
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}
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public static void Ursra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context,
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ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Ursra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context,
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ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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}
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public static void Ushl_V(AILEmitterCtx Context)
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public static void Ushl_V(AILEmitterCtx Context)
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@ -173,41 +197,22 @@ namespace ChocolArm64.Instruction
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public static void Ushr_S(AILEmitterCtx Context)
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public static void Ushr_S(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx);
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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}
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public static void Ushr_V(AILEmitterCtx Context)
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public static void Ushr_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitShrImmOp(Context, ShrImmFlags.VectorZx);
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}
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EmitVectorUnaryOpZx(Context, () =>
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public static void Usra_S(AILEmitterCtx Context)
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{
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Accumulate);
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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}
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public static void Usra_V(AILEmitterCtx Context)
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public static void Usra_V(AILEmitterCtx Context)
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{
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Accumulate);
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Action Emit = () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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Context.Emit(OpCodes.Add);
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};
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EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false);
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}
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}
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private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
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private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
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@ -274,78 +279,118 @@ namespace ChocolArm64.Instruction
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}
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}
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[Flags]
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[Flags]
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private enum ShImmFlags
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private enum ShrImmFlags
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{
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{
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None = 0,
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Scalar = 1 << 0,
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Signed = 1 << 1,
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Signed = 1 << 0,
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Round = 1 << 2,
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Ternary = 1 << 1,
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Accumulate = 1 << 3,
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Rounded = 1 << 2,
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SignedTernary = Signed | Ternary,
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ScalarSx = Scalar | Signed,
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SignedRounded = Signed | Rounded
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ScalarZx = Scalar,
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VectorSx = Signed,
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VectorZx = 0
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}
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}
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private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitScalarShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.Signed);
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx | Flags);
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}
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}
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private static void EmitVectorShImmTernarySx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitScalarShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedTernary);
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx | Flags);
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}
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}
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private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitVectorShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.None);
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EmitShrImmOp(Context, ShrImmFlags.VectorSx | Flags);
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}
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}
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private static void EmitVectorRoundShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm, long Rc)
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private static void EmitVectorShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedRounded, Rc);
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EmitShrImmOp(Context, ShrImmFlags.VectorZx | Flags);
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}
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}
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private static void EmitVectorShImmOp(AILEmitterCtx Context, Action Emit, int Imm, ShImmFlags Flags, long Rc = 0)
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private static void EmitShrImmOp(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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bool Scalar = (Flags & ShrImmFlags.Scalar) != 0;
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bool Signed = (Flags & ShrImmFlags.Signed) != 0;
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bool Round = (Flags & ShrImmFlags.Round) != 0;
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bool Accumulate = (Flags & ShrImmFlags.Accumulate) != 0;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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int Bytes = Op.GetBitsCount() >> 3;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Elems = !Scalar ? Bytes >> Op.Size : 1;
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bool Signed = (Flags & ShImmFlags.Signed) != 0;
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bool Ternary = (Flags & ShImmFlags.Ternary) != 0;
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bool Rounded = (Flags & ShImmFlags.Rounded) != 0;
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for (int Index = 0; Index < Elems; Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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{
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if (Ternary)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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}
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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if (Rounded)
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if (Op.Size <= 2)
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{
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{
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Context.EmitLdc_I8(Rc);
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if (Round)
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Shift);
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Context.Emit(Signed ? OpCodes.Shr : OpCodes.Shr_Un);
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}
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else
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{
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EmitShrImm_64(Context, Signed, Round ? RoundConst : 0L, Shift);
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}
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if (Accumulate)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Add);
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}
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}
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Context.EmitLdc_I4(Imm);
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EmitVectorInsertTmp(Context, Index, Op.Size);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
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{
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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}
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// Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift;
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private static void EmitShrImm_64(
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AILEmitterCtx Context,
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bool Signed,
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long RoundConst,
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int Shift)
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{
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/*if (((AOpCodeSimd)Context.CurrOp).Size < 3)
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{
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throw new InvalidOperationException();
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}*/
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Context.EmitLdc_I8(RoundConst);
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Context.EmitLdc_I4(Shift);
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SignedShrImm_64)
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: nameof(ASoftFallback.UnsignedShrImm_64));
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}
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private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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{
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EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
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EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
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@ -414,4 +459,4 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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Context.EmitStvec(Op.Rd);
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}
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}
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}
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}
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}
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}
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