mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Move division instructions implementation to InstEmitDiv

Browse source
This commit is contained in:
gdkchan 2019-05-29 21:51:28 -03:00
parent 03993e4288
commit 4246257d16
2 changed files with 67 additions and 55 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

55
ARMeilleure/Instructions/InstEmitAlu.cs
View file

@ -267,61 +267,6 @@ namespace ARMeilleure.Instructions
SetAluDOrZR(context, context.RotateRight(GetAluN(context), GetAluMShift(context)));
}
public static void Sdiv(EmitterContext context) => EmitDiv(context, unsigned: false);
public static void Udiv(EmitterContext context) => EmitDiv(context, unsigned: true);
private static void EmitDiv(EmitterContext context, bool unsigned)
{
OpCodeDiv op = (OpCodeDiv)context.CurrOp;
//If Rm == 0, Rd = 0 (division by zero).
Operand n = GetIntOrZR(op, op.Rn);
Operand m = GetIntOrZR(op, op.Rm);
Operand divisorIsZero = context.ICompareEqual(m, Const(m.Type, 0));
Operand lblBadDiv = Label();
Operand lblEnd = Label();
context.BranchIfTrue(lblBadDiv, divisorIsZero);
if (!unsigned)
{
//If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
bool is32Bits = op.RegisterSize == RegisterSize.Int32;
Operand intMin = is32Bits ? Const(int.MinValue) : Const(long.MinValue);
Operand minus1 = is32Bits ? Const(-1) : Const(-1L);
Operand nIsIntMin = context.ICompareEqual(n, intMin);
Operand mIsMinus1 = context.ICompareEqual(m, minus1);
Operand lblGoodDiv = Label();
context.BranchIfFalse(lblGoodDiv, context.BitwiseAnd(nIsIntMin, mIsMinus1));
SetAluDOrZR(context, intMin);
context.Branch(lblEnd);
context.MarkLabel(lblGoodDiv);
}
Operand d = unsigned
? context.IDivideUI(n, m)
: context.IDivide (n, m);
SetAluDOrZR(context, d);
context.Branch(lblEnd);
context.MarkLabel(lblBadDiv);
SetAluDOrZR(context, Const(op.GetOperandType(), 0));
context.MarkLabel(lblEnd);
}
private static Operand GetAluMShift(EmitterContext context)
{
IOpCodeAluRs op = (IOpCodeAluRs)context.CurrOp;

67
ARMeilleure/Instructions/InstEmitDiv.cs Normal file
View file

@ -0,0 +1,67 @@
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
public static void Sdiv(EmitterContext context) => EmitDiv(context, unsigned: false);
public static void Udiv(EmitterContext context) => EmitDiv(context, unsigned: true);
private static void EmitDiv(EmitterContext context, bool unsigned)
{
OpCodeDiv op = (OpCodeDiv)context.CurrOp;
//If Rm == 0, Rd = 0 (division by zero).
Operand n = GetIntOrZR(op, op.Rn);
Operand m = GetIntOrZR(op, op.Rm);
Operand divisorIsZero = context.ICompareEqual(m, Const(m.Type, 0));
Operand lblBadDiv = Label();
Operand lblEnd = Label();
context.BranchIfTrue(lblBadDiv, divisorIsZero);
if (!unsigned)
{
//If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
bool is32Bits = op.RegisterSize == RegisterSize.Int32;
Operand intMin = is32Bits ? Const(int.MinValue) : Const(long.MinValue);
Operand minus1 = is32Bits ? Const(-1) : Const(-1L);
Operand nIsIntMin = context.ICompareEqual(n, intMin);
Operand mIsMinus1 = context.ICompareEqual(m, minus1);
Operand lblGoodDiv = Label();
context.BranchIfFalse(lblGoodDiv, context.BitwiseAnd(nIsIntMin, mIsMinus1));
SetAluDOrZR(context, intMin);
context.Branch(lblEnd);
context.MarkLabel(lblGoodDiv);
}
Operand d = unsigned
? context.IDivideUI(n, m)
: context.IDivide (n, m);
SetAluDOrZR(context, d);
context.Branch(lblEnd);
context.MarkLabel(lblBadDiv);
SetAluDOrZR(context, Const(op.GetOperandType(), 0));
context.MarkLabel(lblEnd);
}
}
}