diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs b/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs index 48efc18fd2..4ccd43dbb9 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs @@ -115,6 +115,22 @@ namespace Ryujinx.Tests.Cpu 0x1E620430u // FCCMPE D1, D2, #0, EQ }; } + + private static uint[] _F_Csel_S_S_() + { + return new uint[] + { + 0x1E220C20u // FCSEL S0, S1, S2, EQ + }; + } + + private static uint[] _F_Csel_S_D_() + { + return new uint[] + { + 0x1E620C20u // FCSEL D0, D1, D2, EQ + }; + } #endregion private const int RndCnt = 2; @@ -173,6 +189,48 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc); } + + [Test, Pairwise] [Explicit] + public void F_Csel_S_S([ValueSource("_F_Csel_S_S_")] uint opcodes, + [ValueSource("_1S_F_")] ulong a, + [ValueSource("_1S_F_")] ulong b, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + opcodes |= ((cond & 15) << 12); + + ulong z = TestContext.CurrentContext.Random.NextULong(); + Vector128 v0 = MakeVectorE0E1(z, z); + Vector128 v1 = MakeVectorE0(a); + Vector128 v2 = MakeVectorE0(b); + + SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] [Explicit] + public void F_Csel_S_D([ValueSource("_F_Csel_S_D_")] uint opcodes, + [ValueSource("_1D_F_")] ulong a, + [ValueSource("_1D_F_")] ulong b, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + opcodes |= ((cond & 15) << 12); + + ulong z = TestContext.CurrentContext.Random.NextULong(); + Vector128 v0 = MakeVectorE1(z); + Vector128 v1 = MakeVectorE0(a); + Vector128 v2 = MakeVectorE0(b); + + SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } #endif } }