mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Add Tbl_V Sse opt..

Browse source
This commit is contained in:
LDj3SNuD 2019-03-18 11:48:54 +01:00 • committed by LDj3SNuD
commit 49dc937a97
1 changed files with 78 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

57
ChocolArm64/Instructions/InstEmitSimdMove.cs
View file

@ -355,6 +355,62 @@ namespace ChocolArm64.Instructions
{ {
OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp; OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp;
if (Optimizations.UseSsse3)
{
Type[] typesCmpSflSub = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
Type[] typesOr = new Type[] { typeof(Vector128<long> ), typeof(Vector128<long> ) };
Type[] typesSav = new Type[] { typeof(long) };
context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm);
context.EmitLdc_I8(0x0F0F0F0F0F0F0F0FL);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.CompareGreaterThan), typesCmpSflSub));
context.EmitLdvec(op.Rm);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesCmpSflSub));
for (int index = 1; index < op.Size; index++)
{
context.EmitLdvec((op.Rn + index) & 0x1F);
context.EmitLdvec(op.Rm);
context.EmitLdc_I8(0x1010101010101010L * index);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesCmpSflSub));
context.EmitStvectmp();
context.EmitLdvectmp();
context.EmitLdc_I8(0x0F0F0F0F0F0F0F0FL);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.CompareGreaterThan), typesCmpSflSub));
context.EmitLdvectmp();
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesCmpSflSub));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
}
context.EmitStvec(op.Rd);
if (op.RegisterSize == RegisterSize.Simd64)
{
EmitVectorZeroUpper(context, op.Rd);
}
}
else
{
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
for (int index = 0; index < op.Size; index++) for (int index = 0; index < op.Size; index++)
@ -385,6 +441,7 @@ namespace ChocolArm64.Instructions
context.EmitStvec(op.Rd); context.EmitStvec(op.Rd);
} }
}
public static void Trn1_V(ILEmitterCtx context) public static void Trn1_V(ILEmitterCtx context)
{ {