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Add Tbl_V Sse opt..

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LDj3SNuD 2019-03-18 11:48:54 +01:00 • committed by LDj3SNuD
commit 49dc937a97
1 changed files with 78 additions and 21 deletions
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99
ChocolArm64/Instructions/InstEmitSimdMove.cs
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@ -355,35 +355,92 @@ namespace ChocolArm64.Instructions
{ {
OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp; OpCodeSimdTbl64 op = (OpCodeSimdTbl64)context.CurrOp;
context.EmitLdvec(op.Rm); if (Optimizations.UseSsse3)
for (int index = 0; index < op.Size; index++)
{ {
context.EmitLdvec((op.Rn + index) & 0x1f); Type[] typesCmpSflSub = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
} Type[] typesOr = new Type[] { typeof(Vector128<long> ), typeof(Vector128<long> ) };
Type[] typesSav = new Type[] { typeof(long) };
switch (op.Size) context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm);
context.EmitLdc_I8(0x0F0F0F0F0F0F0F0FL);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.CompareGreaterThan), typesCmpSflSub));
context.EmitLdvec(op.Rm);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesCmpSflSub));
for (int index = 1; index < op.Size; index++)
{
context.EmitLdvec((op.Rn + index) & 0x1F);
context.EmitLdvec(op.Rm);
context.EmitLdc_I8(0x1010101010101010L * index);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesCmpSflSub));
context.EmitStvectmp();
context.EmitLdvectmp();
context.EmitLdc_I8(0x0F0F0F0F0F0F0F0FL);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.CompareGreaterThan), typesCmpSflSub));
context.EmitLdvectmp();
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesCmpSflSub));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesOr));
}
context.EmitStvec(op.Rd);
if (op.RegisterSize == RegisterSize.Simd64)
{
EmitVectorZeroUpper(context, op.Rd);
}
}
else
{ {
case 1: VectorHelper.EmitCall(context, context.EmitLdvec(op.Rm);
nameof(VectorHelper.Tbl1_V64),
nameof(VectorHelper.Tbl1_V128)); break;
case 2: VectorHelper.EmitCall(context, for (int index = 0; index < op.Size; index++)
nameof(VectorHelper.Tbl2_V64), {
nameof(VectorHelper.Tbl2_V128)); break; context.EmitLdvec((op.Rn + index) & 0x1f);
}
case 3: VectorHelper.EmitCall(context, switch (op.Size)
nameof(VectorHelper.Tbl3_V64), {
nameof(VectorHelper.Tbl3_V128)); break; case 1: VectorHelper.EmitCall(context,
nameof(VectorHelper.Tbl1_V64),
nameof(VectorHelper.Tbl1_V128)); break;
case 4: VectorHelper.EmitCall(context, case 2: VectorHelper.EmitCall(context,
nameof(VectorHelper.Tbl4_V64), nameof(VectorHelper.Tbl2_V64),
nameof(VectorHelper.Tbl4_V128)); break; nameof(VectorHelper.Tbl2_V128)); break;
default: throw new InvalidOperationException(); case 3: VectorHelper.EmitCall(context,
nameof(VectorHelper.Tbl3_V64),
nameof(VectorHelper.Tbl3_V128)); break;
case 4: VectorHelper.EmitCall(context,
nameof(VectorHelper.Tbl4_V64),
nameof(VectorHelper.Tbl4_V128)); break;
default: throw new InvalidOperationException();
}
context.EmitStvec(op.Rd);
} }
context.EmitStvec(op.Rd);
} }
public static void Trn1_V(ILEmitterCtx context) public static void Trn1_V(ILEmitterCtx context)