From 4abff91426fe04e0744fd2084640d137e4d04c94 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 13 Oct 2018 01:09:32 +0200
Subject: [PATCH] Update AInstEmitSimdShift.cs

---
 ChocolArm64/Instruction/AInstEmitSimdShift.cs | 78 +++++++++++++++++--
 1 file changed, 72 insertions(+), 6 deletions(-)

diff --git a/ChocolArm64/Instruction/AInstEmitSimdShift.cs b/ChocolArm64/Instruction/AInstEmitSimdShift.cs
index 127abf1df8..cde1c585ce 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdShift.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdShift.cs
@@ -3,6 +3,7 @@ using ChocolArm64.State;
 using ChocolArm64.Translation;
 using System;
 using System.Reflection.Emit;
+using System.Runtime.Intrinsics.X86;
 
 using static ChocolArm64.Instruction.AInstEmitSimdHelper;
 
@@ -31,12 +32,32 @@ namespace ChocolArm64.Instruction
         {
             AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
 
-            EmitVectorUnaryOpZx(Context, () =>
+            if (AOptimizations.UseSse2 && Op.Size > 0)
             {
-                Context.EmitLdc_I4(GetImmShl(Op));
+                Type[] Types = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
 
-                Context.Emit(OpCodes.Shl);
-            });
+                EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
+
+	            Context.EmitLdc_I4(GetImmShl(Op));
+
+	            Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), Types));
+
+                EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
+
+                if (Op.RegisterSize == ARegisterSize.SIMD64)
+                {
+                    EmitVectorZeroUpper(Context, Op.Rd);
+                }
+            }
+            else
+            {
+                EmitVectorUnaryOpZx(Context, () =>
+                {
+                    Context.EmitLdc_I4(GetImmShl(Op));
+
+                    Context.Emit(OpCodes.Shl);
+                });
+            }
         }
 
         public static void Shll_V(AILEmitterCtx Context)
@@ -167,7 +188,30 @@ namespace ChocolArm64.Instruction
 
         public static void Sshr_V(AILEmitterCtx Context)
         {
-            EmitShrImmOp(Context, ShrImmFlags.VectorSx);
+            AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
+
+            if (AOptimizations.UseSse2 && Op.Size > 0
+                                       && Op.Size < 3)
+            {
+                Type[] Types = new Type[] { VectorIntTypesPerSizeLog2[Op.Size], typeof(byte) };
+
+                EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
+
+	            Context.EmitLdc_I4(GetImmShr(Op));
+
+	            Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), Types));
+
+                EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
+
+                if (Op.RegisterSize == ARegisterSize.SIMD64)
+                {
+                    EmitVectorZeroUpper(Context, Op.Rd);
+                }
+            }
+            else
+            {
+                EmitShrImmOp(Context, ShrImmFlags.VectorSx);
+            }
         }
 
         public static void Ssra_S(AILEmitterCtx Context)
@@ -239,7 +283,29 @@ namespace ChocolArm64.Instruction
 
         public static void Ushr_V(AILEmitterCtx Context)
         {
-            EmitShrImmOp(Context, ShrImmFlags.VectorZx);
+            AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
+
+            if (AOptimizations.UseSse2 && Op.Size > 0)
+            {
+                Type[] Types = new Type[] { VectorUIntTypesPerSizeLog2[Op.Size], typeof(byte) };
+
+                EmitLdvecWithUnsignedCast(Context, Op.Rn, Op.Size);
+
+	            Context.EmitLdc_I4(GetImmShr(Op));
+
+	            Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), Types));
+
+                EmitStvecWithUnsignedCast(Context, Op.Rd, Op.Size);
+
+                if (Op.RegisterSize == ARegisterSize.SIMD64)
+                {
+                    EmitVectorZeroUpper(Context, Op.Rd);
+                }
+            }
+            else
+            {
+                EmitShrImmOp(Context, ShrImmFlags.VectorZx);
+            }
         }
 
         public static void Usra_S(AILEmitterCtx Context)