diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index d32bd9cd24..48791cdca6 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -211,6 +211,7 @@ namespace ChocolArm64
             Set("0>0011100<100001100110xxxxxxxxxx", AInstEmit.Frintm_V,      typeof(AOpCodeSimd));
             Set("000111100x100100110000xxxxxxxxxx", AInstEmit.Frintp_S,      typeof(AOpCodeSimd));
             Set("000111100x100111010000xxxxxxxxxx", AInstEmit.Frintx_S,      typeof(AOpCodeSimd));
+            Set("0>1011100<100001100110xxxxxxxxxx", AInstEmit.Frintx_V,      typeof(AOpCodeSimd)); 
             Set("000111100x100001110000xxxxxxxxxx", AInstEmit.Fsqrt_S,       typeof(AOpCodeSimd));
             Set("000111100x1xxxxx001110xxxxxxxxxx", AInstEmit.Fsub_S,        typeof(AOpCodeSimdReg));
             Set("0>0011101<1xxxxx110101xxxxxxxxxx", AInstEmit.Fsub_V,        typeof(AOpCodeSimdReg));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index bf980a581e..634ac1031a 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -285,6 +285,7 @@ namespace ChocolArm64.Instruction
 
         public static void Frintx_S(AILEmitterCtx Context)
         {
+            Console.WriteLine("Frintx_S");
             AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
 
             EmitScalarUnaryOpF(Context, () =>
@@ -308,6 +309,32 @@ namespace ChocolArm64.Instruction
             });
         }
 
+        public static void Frintx_V(AILEmitterCtx Context)
+        {
+            Console.WriteLine("Frintx_V");
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            EmitVectorUnaryOpF(Context, () =>
+            {
+                Context.EmitLdarg(ATranslatedSub.StateArgIdx);
+
+                Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
+
+                if (Op.Size == 0)
+                {
+                    ASoftFallback.EmitCall(Context, nameof(ASoftFallback.RoundF));
+                }
+                else if (Op.Size == 1)
+                {
+                    ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Round));
+                }
+                else
+                {
+                    throw new InvalidOperationException();
+                }
+            });
+        }
+
         public static void Fsqrt_S(AILEmitterCtx Context)
         {
             EmitScalarUnaryOpF(Context, () =>
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
index ff79cea5aa..2347b8d8f5 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
@@ -127,5 +127,63 @@ namespace Ryujinx.Tests.Cpu
         	AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp);
         	Assert.AreEqual(Result, ThreadState.V0.X0);
         }
+
+        [TestCase(0x3FE66666u, 0x3FE66666u, 'N', false, 0x40000000u, 0x40000000u)]
+        [TestCase(0x3F99999Au, 0x3F99999Au, 'N', false, 0x3F800000u, 0x3F800000u)]
+        [TestCase(0x404CCCCDu, 0x404CCCCDu, 'P', false, 0x40800000u, 0x40800000u)]
+        [TestCase(0x40733333u, 0x40733333u, 'P', false, 0x40800000u, 0x40800000u)]
+        [TestCase(0x404CCCCDu, 0x404CCCCDu, 'M', false, 0x40400000u, 0x40400000u)]
+        [TestCase(0x40733333u, 0x40733333u, 'M', false, 0x40400000u, 0x40400000u)]
+        [TestCase(0x3F99999Au, 0x3F99999Au, 'Z', false, 0x3F800000u, 0x3F800000u)]
+        [TestCase(0x3FE66666u, 0x3FE66666u, 'Z', false, 0x3F800000u, 0x3F800000u)]
+        [TestCase(0x00000000u, 0x00000000u, 'N', false, 0x00000000u, 0x00000000u)]
+        [TestCase(0x00000000u, 0x00000000u, 'P', false, 0x00000000u, 0x00000000u)]
+        [TestCase(0x00000000u, 0x00000000u, 'M', false, 0x00000000u, 0x00000000u)]
+        [TestCase(0x00000000u, 0x00000000u, 'Z', false, 0x00000000u, 0x00000000u)]
+        [TestCase(0x80000000u, 0x80000000u, 'N', false, 0x80000000u, 0x80000000u)]
+        [TestCase(0x80000000u, 0x80000000u, 'P', false, 0x80000000u, 0x80000000u)]
+        [TestCase(0x80000000u, 0x80000000u, 'M', false, 0x80000000u, 0x80000000u)]
+        [TestCase(0x80000000u, 0x80000000u, 'Z', false, 0x80000000u, 0x80000000u)]
+        [TestCase(0x7F800000u, 0x7F800000u, 'N', false, 0x7F800000u, 0x7F800000u)]
+        [TestCase(0x7F800000u, 0x7F800000u, 'P', false, 0x7F800000u, 0x7F800000u)]
+        [TestCase(0x7F800000u, 0x7F800000u, 'M', false, 0x7F800000u, 0x7F800000u)]
+        [TestCase(0x7F800000u, 0x7F800000u, 'Z', false, 0x7F800000u, 0x7F800000u)]
+        [TestCase(0xFF800000u, 0xFF800000u, 'N', false, 0xFF800000u, 0xFF800000u)]
+        [TestCase(0xFF800000u, 0xFF800000u, 'P', false, 0xFF800000u, 0xFF800000u)]
+        [TestCase(0xFF800000u, 0xFF800000u, 'M', false, 0xFF800000u, 0xFF800000u)]
+        [TestCase(0xFF800000u, 0xFF800000u, 'Z', false, 0xFF800000u, 0xFF800000u)]
+        public void Frintx_V(uint A, uint B, char RoundType, bool DefaultNaN, uint Result0, uint Result1)
+        {
+            int FpcrTemp = 0x0;
+            switch(RoundType)
+            {
+                case 'N':
+                FpcrTemp = 0x0;
+                break;
+
+                case 'P':
+                FpcrTemp = 0x400000;
+                break;
+
+                case 'M':
+                FpcrTemp = 0x800000;
+                break;
+
+                case 'Z':
+                FpcrTemp = 0xC00000;
+                break;
+            }
+            if(DefaultNaN)
+            {
+                FpcrTemp |= 1 << 25;
+            }
+            AVec V1 = new AVec { X0 = A, X1 = B };
+            AThreadState ThreadState = SingleOpcode(0x6E619820, V1: V1, Fpcr: FpcrTemp);
+            Assert.Multiple(() =>
+            {
+                Assert.AreEqual(Result0, ThreadState.V0.X0);
+                Assert.AreEqual(Result1, ThreadState.V0.X1);
+            });
+        }
     }
 }