From 520b20fe34e043a0e5a0a7d350efd95d90c90a75 Mon Sep 17 00:00:00 2001 From: riperiperi Date: Wed, 19 Feb 2020 22:50:40 +0000 Subject: [PATCH] Address LDj feedback (minus table flatten) one final look before it's all gone. the world is so beautiful. --- ARMeilleure/Decoders/OpCodeTable.cs | 8 ++++---- .../Instructions/InstEmitSimdArithmetic32.cs | 18 +++++++++--------- ARMeilleure/Instructions/SoftFloat.cs | 1 + Ryujinx.Tests/Cpu/CpuTestAlu32.cs | 1 + Ryujinx.Tests/Cpu/CpuTestAluRs32.cs | 3 ++- Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs | 1 + Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs | 4 +--- Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 8 ++++---- Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | 2 +- 9 files changed, 24 insertions(+), 22 deletions(-) diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs index d03f6a27f0..7c92bdb1c8 100644 --- a/ARMeilleure/Decoders/OpCodeTable.cs +++ b/ARMeilleure/Decoders/OpCodeTable.cs @@ -818,10 +818,10 @@ namespace ARMeilleure.Decoders SetA32("1111001x0x<>x0x0xxxx", InstName.Vmaxnm, InstEmit32.VmaxNm_S, typeof(OpCode32SimdRegS)); - SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm, InstEmit32.VmaxminNm_V, typeof(OpCode32SimdReg)); - SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.VminNm_S, typeof(OpCode32SimdRegS)); - SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm, InstEmit32.VmaxminNm_V, typeof(OpCode32SimdReg)); + SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_S, typeof(OpCode32SimdRegS)); + SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_V, typeof(OpCode32SimdReg)); + SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.Vminnm_S, typeof(OpCode32SimdRegS)); + SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm, InstEmit32.Vminnm_V, typeof(OpCode32SimdReg)); SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla, InstEmit32.Vmla_I, typeof(OpCode32SimdReg)); SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla, InstEmit32.Vmla_S, typeof(OpCode32SimdRegS)); diff --git a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index 8fe2479ccb..4ee279ee0d 100644 --- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -238,24 +238,24 @@ namespace ARMeilleure.Instructions } } - public static void VmaxNm_S(ArmEmitterContext context) + public static void Vmaxnm_S(ArmEmitterContext context) { EmitScalarBinaryOpF32(context, (op1, op2) => EmitSoftFloatCall(context, SoftFloat32.FPMaxNum, SoftFloat64.FPMaxNum, op1, op2)); } - public static void VminNm_S(ArmEmitterContext context) + public static void Vmaxnm_V(ArmEmitterContext context) + { + EmitVectorBinaryOpSx32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMaxNumFpscr, SoftFloat64.FPMaxNumFpscr, op1, op2)); + } + + public static void Vminnm_S(ArmEmitterContext context) { EmitScalarBinaryOpF32(context, (op1, op2) => EmitSoftFloatCall(context, SoftFloat32.FPMinNum, SoftFloat64.FPMinNum, op1, op2)); } - public static void VmaxminNm_V(ArmEmitterContext context) + public static void Vminnm_V(ArmEmitterContext context) { - OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; - bool max = (op.Size & 2) == 0; // Op is high bit of size (not used for fp). - _F32_F32_F32_Bool f32 = max ? new _F32_F32_F32_Bool(SoftFloat32.FPMaxNumFpscr) : new _F32_F32_F32_Bool(SoftFloat32.FPMinNumFpscr); - _F64_F64_F64_Bool f64 = max ? new _F64_F64_F64_Bool(SoftFloat64.FPMaxNumFpscr) : new _F64_F64_F64_Bool(SoftFloat64.FPMinNumFpscr); - - EmitVectorBinaryOpSx32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, f32, f64, op1, op2)); + EmitVectorBinaryOpSx32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMinNumFpscr, SoftFloat64.FPMinNumFpscr, op1, op2)); } public static void Vmax_V(ArmEmitterContext context) diff --git a/ARMeilleure/Instructions/SoftFloat.cs b/ARMeilleure/Instructions/SoftFloat.cs index aa3df0696a..d3e15a2ced 100644 --- a/ARMeilleure/Instructions/SoftFloat.cs +++ b/ARMeilleure/Instructions/SoftFloat.cs @@ -2799,6 +2799,7 @@ namespace ARMeilleure.Instructions { bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + if (inf1 && inf2 && sign1 == sign2) { result = FPDefaultNaN(); diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs index 29663c746e..145417ae2c 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs @@ -9,6 +9,7 @@ namespace Ryujinx.Tests.Cpu public sealed class CpuTestAlu32 : CpuTest32 { #if Alu32 + #region "ValueSource (Opcodes)" private static uint[] _Lsr_Lsl_Asr_Ror_() { diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs index b4d3107654..25b2c96873 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs @@ -8,6 +8,7 @@ namespace Ryujinx.Tests.Cpu public sealed class CpuTestAluRs32 : CpuTest32 { #if AluRs32 + #region "ValueSource (Opcodes)" private static uint[] _Add_Adds_Rsb_Rsbs_() { @@ -32,7 +33,7 @@ namespace Ryujinx.Tests.Cpu 0xe0d00000u // SBCS R0, R0, R0 }; } - #endregion +#endregion private const int RndCnt = 2; private const int RndCntAmount = 2; diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs index 2614d3e8a8..dfbd3b0bdd 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs @@ -10,6 +10,7 @@ namespace Ryujinx.Tests.Cpu public sealed class CpuTestSimdLogical32 : CpuTest32 { #if SimdLogical32 + #region "ValueSource (Opcodes)" private static uint[] _Vbif_Vbit_Vbsl_Vand_() { diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs index 4975c87248..13d6107884 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs @@ -3,8 +3,6 @@ using ARMeilleure.State; using NUnit.Framework; using System; -using System.Collections.Generic; -using System.Text; namespace Ryujinx.Tests.Cpu { @@ -12,7 +10,7 @@ namespace Ryujinx.Tests.Cpu public sealed class CpuTestSimdMov32 : CpuTest32 { #if SimdMov32 - private const int RndCntImm = 10; + private const int RndCntImm = 2; [Test, Pairwise, Description("VMOV.I
, #")] public void Movi_V([Range(0u, 10u)] uint variant, diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 5a29f7b265..a3ba936918 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -8,11 +8,11 @@ using System.Collections.Generic; namespace Ryujinx.Tests.Cpu { [Category("SimdReg32")] - public sealed class CpuTestSimdReg32 : CpuTest32 + public sealed class CpuTestSimdReg32 : CpuTest32 { #if SimdReg32 - #region "ValueSource (Types)" +#region "ValueSource (Types)" private static ulong[] _1B1H1S1D_() { return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful, @@ -199,9 +199,9 @@ namespace Ryujinx.Tests.Cpu yield return rnd2; } } - #endregion +#endregion - private const int RndCnt = 5; + private const int RndCnt = 2; private static readonly bool NoZeros = false; private static readonly bool NoInfs = false; diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs index 0584bb7d98..6c7b0493b9 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu public sealed class CpuTestSimdShImm32 : CpuTest32 { #if SimdShImm32 - private const int RndCnt = 5; + private const int RndCnt = 2; [Test, Pairwise, Description("VSHL. {}, , #")] public void Vshl_Imm([Values(0u)] uint rd,