diff --git a/ChocolArm64/Instructions32/A32InstInterpretFlow.cs b/ChocolArm64/Instructions32/A32InstInterpretFlow.cs
index b839a6d402..d7538af479 100644
--- a/ChocolArm64/Instructions32/A32InstInterpretFlow.cs
+++ b/ChocolArm64/Instructions32/A32InstInterpretFlow.cs
@@ -37,6 +37,21 @@ namespace ChocolArm64.Instructions32
             }
         }
 
+        public static void Bx(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
+        {
+            A32OpCodeBReg op = (A32OpCodeBReg)opCode;
+            if (IsConditionTrue(state, op.Cond))
+            {
+                uint pc = GetPc(state);
+                BXWritePC(state, GetReg(state, op.Rm));
+            }
+        }
+
+        public static void Bxj(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
+        {
+            Bx(state, memory, opCode);
+        }
+
         private static void Blx_Imm(CpuThreadState state, MemoryManager memory, OpCode64 opCode, bool x)
         {
             A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode;
diff --git a/ChocolArm64/OpCodeTable.cs b/ChocolArm64/OpCodeTable.cs
index 263823ab59..73e285056c 100644
--- a/ChocolArm64/OpCodeTable.cs
+++ b/ChocolArm64/OpCodeTable.cs
@@ -18,6 +18,8 @@ namespace ChocolArm64
             SetA32("<<<<1011xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Bl,     typeof(A32OpCodeBImmAl));
             SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Blx,    typeof(A32OpCodeBImmAl));
             SetA32("<<<<000100101111111111110011xxxx", A32InstInterpret.Blx,    typeof(A32OpCodeBReg));
+            SetA32("<<<<000100101111111111110001xxxx", A32InstInterpret.Bx,     typeof(A32OpCodeBReg));
+            SetA32("<<<<000100101111111111110010xxxx", A32InstInterpret.Bxj,    typeof(A32OpCodeBReg));
 #endregion
 
 #region "OpCode Table (AArch64)"