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Implement some ioctl3 required by recent games

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This commit is contained in:
Thog 2019-10-29 01:01:57 +01:00
commit 629fe64dd6
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GPG key ID: 0CD291558FAFDBC6
4 changed files with 98 additions and 40 deletions
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18
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvHostAsGpu/NvHostAsGpuFileDevice.cs
View file

@ -58,6 +58,24 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostAsGpu
return result; return result;
} }
public override NvInternalResult Ioctl3(NvIoctl command, Span<byte> arguments, Span<byte> inlineOutBuffer)
{
NvInternalResult result = NvInternalResult.NotImplemented;
if (command.GetTypeValue() == NvIoctl.NvGpuAsMagic)
{
switch (command.GetNumberValue())
{
case 0x08:
// This is the same as the one in ioctl as inlineOutBuffer is empty.
result = CallIoctlMethod<GetVaRegionsArguments>(GetVaRegions, arguments);
break;
}
}
return result;
}
private NvInternalResult BindChannel(ref BindChannelArguments arguments) private NvInternalResult BindChannel(ref BindChannelArguments arguments)
{ {
Logger.PrintStub(LogClass.ServiceNv); Logger.PrintStub(LogClass.ServiceNv);

108
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvHostCtrlGpu/NvHostCtrlGpuFileDevice.cs
View file

@ -56,6 +56,26 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostCtrlGpu
return result; return result;
} }
public override NvInternalResult Ioctl3(NvIoctl command, Span<byte> arguments, Span<byte> inlineOutBuffer)
{
NvInternalResult result = NvInternalResult.NotImplemented;
if (command.GetTypeValue() == NvIoctl.NvGpuMagic)
{
switch (command.GetNumberValue())
{
case 0x05:
result = CallIoctlMethod<GetCharacteristicsArguments, GpuCharacteristics>(GetCharacteristics, arguments, inlineOutBuffer);
break;
case 0x06:
result = CallIoctlMethod<GetTpcMasksArguments, int>(GetTpcMasks, arguments, inlineOutBuffer);
break;
}
}
return result;
}
public override void Close() public override void Close()
{ {
// TODO // TODO
@ -93,54 +113,68 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostCtrlGpu
private NvInternalResult GetCharacteristics(ref GetCharacteristicsArguments arguments) private NvInternalResult GetCharacteristics(ref GetCharacteristicsArguments arguments)
{ {
arguments.BufferSize = 0xa0; return GetCharacteristics(ref arguments, ref arguments.Characteristics);
}
arguments.Characteristics.Arch = 0x120; private NvInternalResult GetCharacteristics(ref GetCharacteristicsArguments arguments, ref GpuCharacteristics characteristics)
arguments.Characteristics.Impl = 0xb; {
arguments.Characteristics.Rev = 0xa1; arguments.Header.BufferSize = 0xa0;
arguments.Characteristics.NumGpc = 0x1;
arguments.Characteristics.L2CacheSize = 0x40000; characteristics.Arch = 0x120;
arguments.Characteristics.OnBoardVideoMemorySize = 0x0; characteristics.Impl = 0xb;
arguments.Characteristics.NumTpcPerGpc = 0x2; characteristics.Rev = 0xa1;
arguments.Characteristics.BusType = 0x20; characteristics.NumGpc = 0x1;
arguments.Characteristics.BigPageSize = 0x20000; characteristics.L2CacheSize = 0x40000;
arguments.Characteristics.CompressionPageSize = 0x20000; characteristics.OnBoardVideoMemorySize = 0x0;
arguments.Characteristics.PdeCoverageBitCount = 0x1b; characteristics.NumTpcPerGpc = 0x2;
arguments.Characteristics.AvailableBigPageSizes = 0x30000; characteristics.BusType = 0x20;
arguments.Characteristics.GpcMask = 0x1; characteristics.BigPageSize = 0x20000;
arguments.Characteristics.SmArchSmVersion = 0x503; characteristics.CompressionPageSize = 0x20000;
arguments.Characteristics.SmArchSpaVersion = 0x503; characteristics.PdeCoverageBitCount = 0x1b;
arguments.Characteristics.SmArchWarpCount = 0x80; characteristics.AvailableBigPageSizes = 0x30000;
arguments.Characteristics.GpuVaBitCount = 0x28; characteristics.GpcMask = 0x1;
arguments.Characteristics.Reserved = 0x0; characteristics.SmArchSmVersion = 0x503;
arguments.Characteristics.Flags = 0x55; characteristics.SmArchSpaVersion = 0x503;
arguments.Characteristics.TwodClass = 0x902d; characteristics.SmArchWarpCount = 0x80;
arguments.Characteristics.ThreedClass = 0xb197; characteristics.GpuVaBitCount = 0x28;
arguments.Characteristics.ComputeClass = 0xb1c0; characteristics.Reserved = 0x0;
arguments.Characteristics.GpfifoClass = 0xb06f; characteristics.Flags = 0x55;
arguments.Characteristics.InlineToMemoryClass = 0xa140; characteristics.TwodClass = 0x902d;
arguments.Characteristics.DmaCopyClass = 0xb0b5; characteristics.ThreedClass = 0xb197;
arguments.Characteristics.MaxFbpsCount = 0x1; characteristics.ComputeClass = 0xb1c0;
arguments.Characteristics.FbpEnMask = 0x0; characteristics.GpfifoClass = 0xb06f;
arguments.Characteristics.MaxLtcPerFbp = 0x2; characteristics.InlineToMemoryClass = 0xa140;
arguments.Characteristics.MaxLtsPerLtc = 0x1; characteristics.DmaCopyClass = 0xb0b5;
arguments.Characteristics.MaxTexPerTpc = 0x0; characteristics.MaxFbpsCount = 0x1;
arguments.Characteristics.MaxGpcCount = 0x1; characteristics.FbpEnMask = 0x0;
arguments.Characteristics.RopL2EnMask0 = 0x21d70; characteristics.MaxLtcPerFbp = 0x2;
arguments.Characteristics.RopL2EnMask1 = 0x0; characteristics.MaxLtsPerLtc = 0x1;
arguments.Characteristics.ChipName = 0x6230326d67; characteristics.MaxTexPerTpc = 0x0;
arguments.Characteristics.GrCompbitStoreBaseHw = 0x0; characteristics.MaxGpcCount = 0x1;
characteristics.RopL2EnMask0 = 0x21d70;
characteristics.RopL2EnMask1 = 0x0;
characteristics.ChipName = 0x6230326d67;
characteristics.GrCompbitStoreBaseHw = 0x0;
arguments.Characteristics = characteristics;
return NvInternalResult.Success; return NvInternalResult.Success;
} }
private NvInternalResult GetTpcMasks(ref GetTpcMasksArguments arguments) private NvInternalResult GetTpcMasks(ref GetTpcMasksArguments arguments)
{
return GetTpcMasks(ref arguments, ref arguments.TpcMask);
}
private NvInternalResult GetTpcMasks(ref GetTpcMasksArguments arguments, ref int tpcMask)
{ {
if (arguments.MaskBufferSize != 0) if (arguments.MaskBufferSize != 0)
{ {
arguments.TpcMask = 3; tpcMask = 3;
arguments.TpcMask = tpcMask;
} }
return NvInternalResult.Success; return NvInternalResult.Success;
} }

11
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvHostCtrlGpu/Types/GetCharacteristicsArguments.cs
View file

@ -42,11 +42,16 @@ namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostCtrlGpu.Types
public long GrCompbitStoreBaseHw; public long GrCompbitStoreBaseHw;
} }
struct CharacteristicsHeader
{
public long BufferSize;
public long BufferAddress;
}
[StructLayout(LayoutKind.Sequential)] [StructLayout(LayoutKind.Sequential)]
struct GetCharacteristicsArguments struct GetCharacteristicsArguments
{ {
public long BufferSize; public CharacteristicsHeader Header;
public long BufferAddress; public GpuCharacteristics Characteristics;
public GpuCharacteristics Characteristics;
} }
} }

1
Ryujinx.HLE/HOS/Services/Nv/NvDrvServices/NvHostCtrlGpu/Types/GetTpcMasksArguments.cs
View file

@ -2,6 +2,7 @@
namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostCtrlGpu.Types namespace Ryujinx.HLE.HOS.Services.Nv.NvDrvServices.NvHostCtrlGpu.Types
{ {
[StructLayout(LayoutKind.Sequential)] [StructLayout(LayoutKind.Sequential)]
struct GetTpcMasksArguments struct GetTpcMasksArguments
{ {