Update ASoftFloat.cs
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1 changed files with 25 additions and 183 deletions
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@ -239,61 +239,21 @@ namespace ChocolArm64.Instruction
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return Result;
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}
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private enum FPType
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{
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Nonzero,
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Zero,
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Infinity,
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QNaN,
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SNaN
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}
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private enum FPExc
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{
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InvalidOp,
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DivideByZero,
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Overflow,
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Underflow,
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Inexact,
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InputDenorm = 7
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}
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private enum FPRounding
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{
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TIEEVEN,
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POSINF,
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NEGINF,
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ZERO
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};
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private enum FPCR
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{
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UFE = 11,
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RMode = 22,
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FZ = 24,
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DN = 25,
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AHP = 26
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPDefaultNaN()
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{
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return -float.NaN;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPInfinity(bool Sign)
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{
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return Sign ? float.NegativeInfinity : float.PositiveInfinity;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPZero(bool Sign)
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{
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return Sign ? -0f : +0f;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPMaxNormal(bool Sign)
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{
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return Sign ? float.MinValue : float.MaxValue;
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@ -345,8 +305,6 @@ namespace ChocolArm64.Instruction
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private static float FPRoundCV(double Real, AThreadState State)
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{
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const int UFCBit = 3; // Underflow cumulative floating-point exception bit.
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const int MinimumExp = -126;
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const int E = 8;
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@ -382,13 +340,17 @@ namespace ChocolArm64.Instruction
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if (State.GetFpcrFlag(FPCR.FZ) && Exponent < MinimumExp)
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{
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State.Fpsr |= 1 << UFCBit;
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State.SetFpsrFlag(FPSR.UFC);
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return FPZero(Sign);
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}
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uint BiasedExp = (uint)Max(Exponent - MinimumExp + 1, 0);
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if (BiasedExp == 0u) Mantissa /= Math.Pow(2d, MinimumExp - Exponent);
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uint BiasedExp = (uint)Math.Max(Exponent - MinimumExp + 1, 0);
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if (BiasedExp == 0u)
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{
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Mantissa /= Math.Pow(2d, MinimumExp - Exponent);
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}
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uint IntMant = (uint)Math.Floor(Mantissa * Math.Pow(2d, F));
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double Error = Mantissa * Math.Pow(2d, F) - (double)IntMant;
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@ -401,25 +363,25 @@ namespace ChocolArm64.Instruction
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bool OverflowToInf;
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bool RoundUp;
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switch (FPRoundingMode(State))
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switch (State.FPRoundingMode())
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{
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default:
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case FPRounding.TIEEVEN:
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case ARoundMode.ToNearest:
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RoundUp = (Error > 0.5d || (Error == 0.5d && (IntMant & 1u) == 1u));
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OverflowToInf = true;
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break;
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case FPRounding.POSINF:
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case ARoundMode.TowardsPlusInfinity:
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RoundUp = (Error != 0d && !Sign);
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OverflowToInf = !Sign;
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break;
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case FPRounding.NEGINF:
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case ARoundMode.TowardsMinusInfinity:
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RoundUp = (Error != 0d && Sign);
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OverflowToInf = Sign;
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break;
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case FPRounding.ZERO:
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case ARoundMode.TowardsZero:
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RoundUp = false;
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OverflowToInf = false;
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break;
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@ -463,11 +425,8 @@ namespace ChocolArm64.Instruction
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}
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return Result;
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int Max(int Left, int Right) => Left >= Right ? Left : Right;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPConvertNaN(ushort ValueBits)
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{
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return BitConverter.Int32BitsToSingle(
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@ -487,18 +446,6 @@ namespace ChocolArm64.Instruction
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State.Fpsr |= 1 << (int)Exc;
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static FPRounding FPRoundingMode(AThreadState State)
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{
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return (FPRounding)((State.Fpcr >> (int)FPCR.RMode) & 3);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static bool GetFpcrFlag(this AThreadState State, FPCR Fpcr)
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{
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return (State.Fpcr & (1 << (int)Fpcr)) != 0;
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}
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}
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static class ASoftFloat32_16
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@ -558,61 +505,21 @@ namespace ChocolArm64.Instruction
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return ResultBits;
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}
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private enum FPType
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{
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Nonzero,
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Zero,
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Infinity,
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QNaN,
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SNaN
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}
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private enum FPExc
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{
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InvalidOp,
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DivideByZero,
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Overflow,
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Underflow,
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Inexact,
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InputDenorm = 7
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}
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private enum FPRounding
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{
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TIEEVEN,
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POSINF,
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NEGINF,
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ZERO
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};
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private enum FPCR
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{
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UFE = 11,
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RMode = 22,
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FZ = 24,
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DN = 25,
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AHP = 26
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static ushort FPDefaultNaN()
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{
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return (ushort)0x7E00u;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static ushort FPInfinity(bool Sign)
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{
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return Sign ? (ushort)0xFC00u : (ushort)0x7C00u;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static ushort FPZero(bool Sign)
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{
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return Sign ? (ushort)0x8000u : (ushort)0x0000u;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static ushort FPMaxNormal(bool Sign)
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{
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return Sign ? (ushort)0xFBFFu : (ushort)0x7BFFu;
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@ -701,8 +608,12 @@ namespace ChocolArm64.Instruction
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Exponent++;
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}
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uint BiasedExp = (uint)Max(Exponent - MinimumExp + 1, 0);
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if (BiasedExp == 0u) Mantissa /= Math.Pow(2d, MinimumExp - Exponent);
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uint BiasedExp = (uint)Math.Max(Exponent - MinimumExp + 1, 0);
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if (BiasedExp == 0u)
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{
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Mantissa /= Math.Pow(2d, MinimumExp - Exponent);
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}
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uint IntMant = (uint)Math.Floor(Mantissa * Math.Pow(2d, F));
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double Error = Mantissa * Math.Pow(2d, F) - (double)IntMant;
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@ -715,25 +626,25 @@ namespace ChocolArm64.Instruction
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bool OverflowToInf;
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bool RoundUp;
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switch (FPRoundingMode(State))
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switch (State.FPRoundingMode())
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{
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default:
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case FPRounding.TIEEVEN:
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case ARoundMode.ToNearest:
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RoundUp = (Error > 0.5d || (Error == 0.5d && (IntMant & 1u) == 1u));
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OverflowToInf = true;
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break;
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case FPRounding.POSINF:
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case ARoundMode.TowardsPlusInfinity:
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RoundUp = (Error != 0d && !Sign);
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OverflowToInf = !Sign;
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break;
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case FPRounding.NEGINF:
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case ARoundMode.TowardsMinusInfinity:
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RoundUp = (Error != 0d && Sign);
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OverflowToInf = Sign;
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break;
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case FPRounding.ZERO:
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case ARoundMode.TowardsZero:
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RoundUp = false;
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OverflowToInf = false;
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break;
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@ -794,11 +705,8 @@ namespace ChocolArm64.Instruction
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}
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return ResultBits;
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int Max(int Left, int Right) => Left >= Right ? Left : Right;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static ushort FPConvertNaN(uint ValueBits)
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{
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return (ushort)((ValueBits & 0x80000000u) >> 16 | 0x7E00u | (ValueBits & 0x003FE000u) >> 13);
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@ -817,18 +725,6 @@ namespace ChocolArm64.Instruction
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State.Fpsr |= 1 << (int)Exc;
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}
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static FPRounding FPRoundingMode(AThreadState State)
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{
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return (FPRounding)((State.Fpcr >> (int)FPCR.RMode) & 3);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static bool GetFpcrFlag(this AThreadState State, FPCR Fpcr)
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{
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return (State.Fpcr & (1 << (int)Fpcr)) != 0;
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}
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}
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static class ASoftFloat_32
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@ -1354,56 +1250,31 @@ namespace ChocolArm64.Instruction
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return Result;
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}
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private enum FPType
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{
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Nonzero,
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Zero,
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Infinity,
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QNaN,
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SNaN
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}
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private enum FPExc
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{
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InvalidOp,
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DivideByZero,
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Overflow,
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Underflow,
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Inexact,
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InputDenorm = 7
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPDefaultNaN()
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{
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return -float.NaN;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPInfinity(bool Sign)
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{
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return Sign ? float.NegativeInfinity : float.PositiveInfinity;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPZero(bool Sign)
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{
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return Sign ? -0f : +0f;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPTwo(bool Sign)
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{
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return Sign ? -2f : +2f;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPOnePointFive(bool Sign)
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{
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return Sign ? -1.5f : +1.5f;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static float FPNeg(this float Value)
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{
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return -Value;
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@ -1525,8 +1396,6 @@ namespace ChocolArm64.Instruction
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private static float FPProcessNaN(FPType Type, uint Op, AThreadState State)
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{
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const int DNBit = 25; // Default NaN mode control bit.
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if (Type == FPType.SNaN)
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{
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Op |= 1u << 22;
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@ -1534,7 +1403,7 @@ namespace ChocolArm64.Instruction
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FPProcessException(FPExc.InvalidOp, State);
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}
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if ((State.Fpcr & (1 << DNBit)) != 0)
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if (State.GetFpcrFlag(FPCR.DN))
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{
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return FPDefaultNaN();
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}
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@ -2080,56 +1949,31 @@ namespace ChocolArm64.Instruction
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return Result;
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}
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private enum FPType
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{
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Nonzero,
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Zero,
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Infinity,
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QNaN,
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SNaN
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}
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private enum FPExc
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{
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InvalidOp,
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DivideByZero,
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Overflow,
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Underflow,
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Inexact,
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InputDenorm = 7
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static double FPDefaultNaN()
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{
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return -double.NaN;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static double FPInfinity(bool Sign)
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{
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return Sign ? double.NegativeInfinity : double.PositiveInfinity;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static double FPZero(bool Sign)
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{
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return Sign ? -0d : +0d;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static double FPTwo(bool Sign)
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{
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return Sign ? -2d : +2d;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static double FPOnePointFive(bool Sign)
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{
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return Sign ? -1.5d : +1.5d;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private static double FPNeg(this double Value)
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{
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return -Value;
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@ -2251,8 +2095,6 @@ namespace ChocolArm64.Instruction
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private static double FPProcessNaN(FPType Type, ulong Op, AThreadState State)
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{
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const int DNBit = 25; // Default NaN mode control bit.
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if (Type == FPType.SNaN)
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{
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Op |= 1ul << 51;
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@ -2260,7 +2102,7 @@ namespace ChocolArm64.Instruction
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FPProcessException(FPExc.InvalidOp, State);
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}
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if ((State.Fpcr & (1 << DNBit)) != 0)
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if (State.GetFpcrFlag(FPCR.DN))
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{
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return FPDefaultNaN();
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}
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