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Fix some issues with shift instructions

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This commit is contained in:
gdkchan 2019-05-30 13:16:10 -03:00
parent c170e0f01c
commit 647d13cb61
3 changed files with 22 additions and 3 deletions
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2
ARMeilleure/CodeGen/X86/Assembler.cs
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@ -380,6 +380,8 @@ namespace ARMeilleure.CodeGen.X86
{
throw new ArgumentException($"Invalid shift register \"{shiftReg}\".");
}
source = null;
}
WriteInstruction(dest, source, inst);

19
ARMeilleure/Instructions/InstEmitAlu.cs
View file

@ -22,7 +22,14 @@ namespace ARMeilleure.Instructions
Operand d = context.IAdd(n, m);
d = context.IAdd(d, GetFlag(PState.CFlag));
Operand carry = GetFlag(PState.CFlag);
if (context.CurrOp.RegisterSize == RegisterSize.Int64)
{
carry = context.Copy(Local(OperandType.I64), carry);
}
d = context.IAdd(d, carry);
if (setFlags)
{
@ -193,6 +200,11 @@ namespace ARMeilleure.Instructions
Operand borrow = context.BitwiseExclusiveOr(GetFlag(PState.CFlag), Const(1));
if (context.CurrOp.RegisterSize == RegisterSize.Int64)
{
borrow = context.Copy(Local(OperandType.I64), borrow);
}
d = context.ISubtract(d, borrow);
if (setFlags)
@ -273,6 +285,11 @@ namespace ARMeilleure.Instructions
Operand m = GetIntOrZR(op, op.Rm);
if (op.RegisterSize == RegisterSize.Int64)
{
m = context.Copy(Local(OperandType.I32), m);
}
return context.BitwiseAnd(m, Const(context.CurrOp.GetBitsCount() - 1));
}

4
ARMeilleure/Translation/EmitterContext.cs
View file

@ -91,9 +91,9 @@ namespace ARMeilleure.Translation
return Add(Instruction.Copy, Local(a.Type), a);
}
public void Copy(Operand d, Operand a)
public Operand Copy(Operand d, Operand a)
{
Add(Instruction.Copy, d, a);
return Add(Instruction.Copy, d, a);
}
public Operand CountLeadingZeros(Operand a)