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Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

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This commit is contained in:
gdkchan 2019-06-13 13:30:33 -03:00
commit 6dd580e9d4
3 changed files with 10 additions and 5 deletions
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2
ARMeilleure/CodeGen/X86/Assembler.cs
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@ -167,7 +167,7 @@ namespace ARMeilleure.CodeGen.X86
Add(X86Instruction.Pshufd, new InstInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f70, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Pshufd, new InstInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f70, InstFlags.Vex | InstFlags.Prefix66));
Add(X86Instruction.Pslldq, new InstInfo(BadOp, 0x07000f73, BadOp, BadOp, BadOp, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Pslldq, new InstInfo(BadOp, 0x07000f73, BadOp, BadOp, BadOp, InstFlags.Vex | InstFlags.Prefix66));
Add(X86Instruction.Psllw, new InstInfo(BadOp, 0x06000f71, BadOp, BadOp, 0x00000ff1, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Psllw, new InstInfo(BadOp, 0x06000f71, BadOp, BadOp, 0x00000ff1, InstFlags.Vex | InstFlags.Prefix66));
Add(X86Instruction.Psrad, new InstInfo(BadOp, 0x00000f72, BadOp, BadOp, 0x00000fe2, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Psrad, new InstInfo(BadOp, 0x04000f72, BadOp, BadOp, 0x00000fe2, InstFlags.Vex | InstFlags.Prefix66));
Add(X86Instruction.Psraw, new InstInfo(BadOp, 0x04000f71, BadOp, BadOp, 0x00000fe1, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Psraw, new InstInfo(BadOp, 0x04000f71, BadOp, BadOp, 0x00000fe1, InstFlags.Vex | InstFlags.Prefix66));
Add(X86Instruction.Psrld, new InstInfo(BadOp, 0x02000f72, BadOp, BadOp, 0x00000fd2, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Psrld, new InstInfo(BadOp, 0x02000f72, BadOp, BadOp, 0x00000fd2, InstFlags.Vex | InstFlags.Prefix66));
Add(X86Instruction.Psrlq, new InstInfo(BadOp, 0x02000f73, BadOp, BadOp, 0x00000fd3, InstFlags.Vex | InstFlags.Prefix66)); Add(X86Instruction.Psrlq, new InstInfo(BadOp, 0x02000f73, BadOp, BadOp, 0x00000fd3, InstFlags.Vex | InstFlags.Prefix66));

2
ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
View file

@ -3153,7 +3153,7 @@ namespace ARMeilleure.Instructions
Operand onesMask = X86GetAllElements(context, -1L); Operand onesMask = X86GetAllElements(context, -1L);
cmpMask = context.AddIntrinsic(Instruction.X86Pand, cmpMask, onesMask); cmpMask = context.AddIntrinsic(Instruction.X86Pandn, cmpMask, onesMask);
Instruction subInst = X86PsubInstruction[size]; Instruction subInst = X86PsubInstruction[size];

11
ARMeilleure/Instructions/InstEmitSimdMove.cs
View file

@ -567,13 +567,13 @@ namespace ARMeilleure.Instructions
if (Optimizations.UseSsse3) if (Optimizations.UseSsse3)
{ {
long maskE0 = _masksE0_TrnUzpXtn[op.Size];
long maskE1 = _masksE1_TrnUzp [op.Size];
Operand mask = null; Operand mask = null;
if (op.Size < 3) if (op.Size < 3)
{ {
long maskE0 = _masksE0_TrnUzpXtn[op.Size];
long maskE1 = _masksE1_TrnUzp [op.Size];
mask = X86GetScalar(context, maskE0); mask = X86GetScalar(context, maskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
@ -599,6 +599,11 @@ namespace ARMeilleure.Instructions
Operand res = context.AddIntrinsic(punpckInst, n, m); Operand res = context.AddIntrinsic(punpckInst, n, m);
if (op.RegisterSize == RegisterSize.Simd64)
{
res = context.VectorZeroUpper64(res);
}
context.Copy(GetVec(op.Rd), res); context.Copy(GetVec(op.Rd), res);
} }
else else