Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions
This commit is contained in:
gdkchan
parent
97ca974213
commit
6e4aeff9e2
4 changed files with 198 additions and 86 deletions
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@ -371,11 +371,15 @@ namespace ChocolArm64
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SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Sminp_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Smlsl_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
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SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
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SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
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SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
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SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
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SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
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SetA64("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
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@ -190,84 +190,6 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitSaturatingExtNarrow(AILEmitterCtx Context, bool SignedSrc, bool SignedDst, bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = (!Scalar ? 8 >> Op.Size : 1);
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int ESize = 8 << Op.Size;
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int Part = (!Scalar & (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0);
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int TMaxValue = (SignedDst ? (1 << (ESize - 1)) - 1 : (int)((1L << ESize) - 1L));
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int TMinValue = (SignedDst ? -((1 << (ESize - 1))) : 0);
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Context.EmitLdc_I8(0L);
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Context.EmitSttmp();
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for (int Index = 0; Index < Elems; Index++)
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{
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AILLabel LblLe = new AILLabel();
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AILLabel LblGeEnd = new AILLabel();
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(TMaxValue);
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Context.Emit(OpCodes.Conv_U8);
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Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I4(TMaxValue);
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Context.EmitLdc_I8(0x8000000L);
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Context.EmitSttmp();
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Context.Emit(OpCodes.Br_S, LblGeEnd);
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Context.MarkLabel(LblLe);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(TMinValue);
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Context.Emit(OpCodes.Conv_I8);
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Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I4(TMinValue);
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Context.EmitLdc_I8(0x8000000L);
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Context.EmitSttmp();
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Context.MarkLabel(LblGeEnd);
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if (Scalar)
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{
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EmitVectorZeroLower(Context, Op.Rd);
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}
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EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
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}
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Conv_I4);
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Context.Emit(OpCodes.Or);
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Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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}
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public static void Fabd_S(AILEmitterCtx Context)
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{
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EmitScalarBinaryOpF(Context, () =>
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@ -1174,6 +1096,15 @@ namespace ChocolArm64.Instruction
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});
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}
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public static void Smlsl_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmTernaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Sub);
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});
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}
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public static void Smull_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Mul));
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@ -1181,22 +1112,22 @@ namespace ChocolArm64.Instruction
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public static void Sqxtn_S(AILEmitterCtx Context)
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{
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: true);
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EmitScalarSaturatingNarrowOpSxSx(Context, () => { });
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}
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public static void Sqxtn_V(AILEmitterCtx Context)
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{
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: true, Scalar: false);
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EmitVectorSaturatingNarrowOpSxSx(Context, () => { });
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}
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public static void Sqxtun_S(AILEmitterCtx Context)
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{
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: true);
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EmitScalarSaturatingNarrowOpSxZx(Context, () => { });
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}
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public static void Sqxtun_V(AILEmitterCtx Context)
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{
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EmitSaturatingExtNarrow(Context, SignedSrc: true, SignedDst: false, Scalar: false);
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EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
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}
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public static void Sub_S(AILEmitterCtx Context)
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@ -1344,12 +1275,12 @@ namespace ChocolArm64.Instruction
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public static void Uqxtn_S(AILEmitterCtx Context)
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{
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EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: true);
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EmitScalarSaturatingNarrowOpZxZx(Context, () => { });
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}
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public static void Uqxtn_V(AILEmitterCtx Context)
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{
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EmitSaturatingExtNarrow(Context, SignedSrc: false, SignedDst: false, Scalar: false);
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EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
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}
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}
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}
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@ -3,6 +3,7 @@ using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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@ -719,7 +720,7 @@ namespace ChocolArm64.Instruction
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EmitVectorPairwiseOp(Context, Emit, false);
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}
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private static void EmitVectorPairwiseOp(AILEmitterCtx Context, Action Emit, bool Signed)
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public static void EmitVectorPairwiseOp(AILEmitterCtx Context, Action Emit, bool Signed)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -749,6 +750,117 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void EmitScalarSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, true, true, true);
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}
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public static void EmitScalarSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, true, false, true);
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}
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public static void EmitScalarSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, false, false, true);
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}
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public static void EmitVectorSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, true, true, false);
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}
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public static void EmitVectorSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, true, false, false);
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}
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public static void EmitVectorSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
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{
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EmitSaturatingNarrowOp(Context, Emit, false, false, false);
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}
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public static void EmitSaturatingNarrowOp(
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AILEmitterCtx Context,
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Action Emit,
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bool SignedSrc,
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bool SignedDst,
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bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = !Scalar ? 8 >> Op.Size : 1;
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int ESize = 8 << Op.Size;
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int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
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long TMaxValue = SignedDst ? (1 << (ESize - 1)) - 1 : (1L << ESize) - 1L;
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long TMinValue = SignedDst ? -((1 << (ESize - 1))) : 0;
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Context.EmitLdc_I8(0L);
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Context.EmitSttmp();
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for (int Index = 0; Index < Elems; Index++)
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{
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AILLabel LblLe = new AILLabel();
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AILLabel LblGeEnd = new AILLabel();
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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Emit();
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I8(TMaxValue);
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Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I8(TMaxValue);
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Context.EmitLdc_I8(0x8000000L);
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Context.EmitSttmp();
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Context.Emit(OpCodes.Br_S, LblGeEnd);
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Context.MarkLabel(LblLe);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I8(TMinValue);
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Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I8(TMinValue);
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Context.EmitLdc_I8(0x8000000L);
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Context.EmitSttmp();
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Context.MarkLabel(LblGeEnd);
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if (Scalar)
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{
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EmitVectorZeroLower(Context, Op.Rd);
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}
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EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
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}
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Conv_I4);
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Context.Emit(OpCodes.Or);
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Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
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}
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public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
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{
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EmitVectorZeroAll(Context, Reg);
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@ -58,7 +58,7 @@ namespace ChocolArm64.Instruction
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int Shift = Op.Imm - (8 << Op.Size);
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ulong Mask = Shift != 0 ? ulong.MaxValue >> (64 - Shift) : 0;
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ulong Mask = Shift != 0 ? ulong.MaxValue >> (64 - Shift) : 0;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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@ -84,6 +84,39 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void Sqrshrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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long RoundConst = 1L << (Shift - 1);
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Action Emit = () =>
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shr);
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};
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EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
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}
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public static void Srshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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long RoundConst = 1L << (Shift - 1);
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EmitVectorRoundShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift, RoundConst);
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}
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public static void Sshl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: true);
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@ -294,6 +327,38 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorRoundShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm, long Rc)
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{
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EmitVectorRoundShImmOp(Context, Emit, Imm, Rc, true);
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}
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private static void EmitVectorRoundShImmOp(AILEmitterCtx Context, Action Emit, int Imm, long Rc, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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Context.EmitLdc_I8(Rc);
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Context.Emit(OpCodes.Add);
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Context.EmitLdc_I4(Imm);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
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