diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs index 23215dd85e..1cd1d14646 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs @@ -30,7 +30,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("LSRS {,} , ")] public void Lsr([Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, [Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount) { uint opcode = 0xe1b00030; // LSRS R0, R0, R0 @@ -46,7 +46,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("LSLS {,} , ")] public void Lsl([Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, [Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount) { uint opcode = 0xe1b00010; // LSLS R0, R0, R0 @@ -62,7 +62,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("ASRS {,} , ")] public void Asr([Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, [Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount) { uint opcode = 0xe1b00050; // ASRS R0, R0, R0 @@ -78,7 +78,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("RORS {,} , ")] public void Ror([Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, [Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount) { uint opcode = 0xe1b00070; // RORS R0, R0, R0 diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs index 508f78a1dc..c1ab334d37 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs @@ -14,13 +14,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("ADC , , ")] public void Adc([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values] bool carryIn) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values] bool carryIn) { uint opcode = 0xe0a00000; // ADC R0, R0, R0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -34,13 +34,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("ADCS , , ")] public void Adcs([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values] bool carryIn) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values] bool carryIn) { uint opcode = 0xe0b00000; // ADCS R0, R0, R0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -54,14 +54,14 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("ADD , , {, #}")] public void Add([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint opcode = 0xe0800000; // ADD R0, R0, R0, LSL #0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -76,14 +76,14 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("ADDS , , {, #}")] public void Adds([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint opcode = 0xe0900000; // ADDS R0, R0, R0, LSL #0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -98,14 +98,14 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("RSB , , {, #}")] public void Rsb([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint opcode = 0xe0600000; // RSB R0, R0, R0, LSL #0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -120,14 +120,14 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("RSBS , , {, #}")] public void Rsbs([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint opcode = 0xe0700000; // RSBS R0, R0, R0, LSL #0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -142,13 +142,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("RSB , , ")] public void Rsc([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values] bool carryIn) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values] bool carryIn) { uint opcode = 0xe0e00000; // RSC R0, R0, R0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -162,13 +162,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("RSCS , , ")] public void Rscs([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values] bool carryIn) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values] bool carryIn) { uint opcode = 0xe0f00000; // RSCS R0, R0, R0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -182,13 +182,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("SBC , , ")] public void Sbc([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values] bool carryIn) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values] bool carryIn) { uint opcode = 0xe0c00000; // SBC R0, R0, R0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -202,13 +202,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("SBCS , , ")] public void Sbcs([Values(0u, 13u)] uint rd, - [Values(1u, 13u)] uint rn, - [Values(2u, 13u)] uint rm, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values] bool carryIn) + [Values(1u, 13u)] uint rn, + [Values(2u, 13u)] uint rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + [Values] bool carryIn) { uint opcode = 0xe0d00000; // SBCS R0, R0, R0 opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); diff --git a/Ryujinx.Tests/Cpu/CpuTestBf32.cs b/Ryujinx.Tests/Cpu/CpuTestBf32.cs index c7865c6172..969c91b4ae 100644 --- a/Ryujinx.Tests/Cpu/CpuTestBf32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestBf32.cs @@ -55,12 +55,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("UBFX , , #, #")] public void Ubfx([Values(0u, 0xdu)] uint rd, - [Values(1u, 0xdu)] uint rn, - [Random(RndCnt)] uint wd, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1) + [Values(1u, 0xdu)] uint rn, + [Random(RndCnt)] uint wd, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1) { if (lsb + widthm1 > 31) { @@ -80,12 +80,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("SBFX , , #, #")] public void Sbfx([Values(0u, 0xdu)] uint rd, - [Values(1u, 0xdu)] uint rn, - [Random(RndCnt)] uint wd, - [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1) + [Values(1u, 0xdu)] uint rn, + [Random(RndCnt)] uint wd, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint lsb, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint widthm1) { if (lsb + widthm1 > 31) { diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs index 56585bc004..0c82e96a4b 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs @@ -34,12 +34,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VBIF {}, , ")] public void Vbif([Range(0u, 4u)] uint rd, - [Range(0u, 4u)] uint rn, - [Range(0u, 4u)] uint rm, - [Random(RndCnt)] ulong z, - [Random(RndCnt)] ulong a, - [Random(RndCnt)] ulong b, - [Values] bool q) + [Range(0u, 4u)] uint rn, + [Range(0u, 4u)] uint rm, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool q) { uint opcode = GenerateVectorOpcode(0xf3300110, rd, rn, rm, q); @@ -54,12 +54,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VBIT {}, , ")] public void Vbit([Range(0u, 4u)] uint rd, - [Range(0u, 4u)] uint rn, - [Range(0u, 4u)] uint rm, - [Random(RndCnt)] ulong z, - [Random(RndCnt)] ulong a, - [Random(RndCnt)] ulong b, - [Values] bool q) + [Range(0u, 4u)] uint rn, + [Range(0u, 4u)] uint rm, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool q) { uint opcode = GenerateVectorOpcode(0xf3200110, rd, rn, rm, q); @@ -74,12 +74,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VBSL {}, , ")] public void Vbsl([Range(0u, 4u)] uint rd, - [Range(0u, 4u)] uint rn, - [Range(0u, 4u)] uint rm, - [Random(RndCnt)] ulong z, - [Random(RndCnt)] ulong a, - [Random(RndCnt)] ulong b, - [Values] bool q) + [Range(0u, 4u)] uint rn, + [Range(0u, 4u)] uint rm, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool q) { uint opcode = GenerateVectorOpcode(0xf3100110, rd, rn, rm, q); @@ -94,12 +94,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VAND {}, , ")] public void Vand([Range(0u, 4u)] uint rd, - [Range(0u, 4u)] uint rn, - [Range(0u, 4u)] uint rm, - [Random(RndCnt)] ulong z, - [Random(RndCnt)] ulong a, - [Random(RndCnt)] ulong b, - [Values] bool q) + [Range(0u, 4u)] uint rn, + [Range(0u, 4u)] uint rm, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool q) { uint opcode = GenerateVectorOpcode(0xf2000110, rd, rn, rm, q); diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs index e8ab243155..49903ea859 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs @@ -39,12 +39,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VLDn. , [ {:}]{ /!/, } (single n element structure)")] public void Vldn_Single([Values(0u, 1u, 2u)] uint size, - [Values(0u, 13u)] uint rn, - [Values(1u, 13u, 15u)] uint rm, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, - [Range(0u, 7u)] uint index, - [Range(0u, 3u)] uint n, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) + [Values(0u, 13u)] uint rn, + [Values(1u, 13u, 15u)] uint rm, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, + [Range(0u, 7u)] uint index, + [Range(0u, 3u)] uint n, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -69,12 +69,12 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VLDn. , [ {:}]{ /!/, } (all lanes)")] public void Vldn_All([Values(0u, 13u)] uint rn, - [Values(1u, 13u, 15u)] uint rm, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, - [Range(0u, 3u)] uint n, - [Range(0u, 2u)] uint size, - [Values] bool t, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) + [Values(1u, 13u, 15u)] uint rm, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, + [Range(0u, 3u)] uint n, + [Range(0u, 2u)] uint size, + [Values] bool t, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -96,11 +96,11 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VLDn. , [ {:}]{ /!/, } (multiple n element structures)")] public void Vldn_Pair([Values(0u, 1u, 2u, 3u)] uint size, - [Values(0u, 13u)] uint rn, - [Values(1u, 13u, 15u)] uint rm, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, - [Range(0u, 3u)] uint mode, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) + [Values(0u, 13u)] uint rn, + [Values(1u, 13u, 15u)] uint rm, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, + [Range(0u, 3u)] uint mode, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -119,12 +119,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VSTn. , [ {:}]{ /!/, } (single n element structure)")] public void Vstn_Single([Values(0u, 1u, 2u)] uint size, - [Values(0u, 13u)] uint rn, - [Values(1u, 13u, 15u)] uint rm, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, - [Range(0u, 7u)] uint index, - [Range(0u, 3u)] uint n, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) + [Values(0u, 13u)] uint rn, + [Values(1u, 13u, 15u)] uint rm, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, + [Range(0u, 7u)] uint index, + [Range(0u, 3u)] uint n, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -151,11 +151,11 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VSTn. , [ {:}]{ /!/, } (multiple n element structures)")] public void Vstn_Pair([Values(0u, 1u, 2u, 3u)] uint size, - [Values(0u, 13u)] uint rn, - [Values(1u, 13u, 15u)] uint rm, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, - [Range(0u, 3u)] uint mode, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) + [Values(0u, 13u)] uint rn, + [Values(1u, 13u, 15u)] uint rm, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, + [Range(0u, 3u)] uint mode, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -176,10 +176,10 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VLDM. {!}, ")] public void Vldm([Values(0u, 13u)] uint rn, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, - [Range(0u, 2u)] uint mode, - [Values(0x1u, 0x32u)] [Random(2u, 31u, RndCntImm)] uint regs, - [Values] bool single) + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd, + [Range(0u, 2u)] uint mode, + [Values(0x1u, 0x32u)] [Random(2u, 31u, RndCntImm)] uint regs, + [Values] bool single) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -223,10 +223,10 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VLDR. , [ {, #{+/-}}]")] public void Vldr([Values(2u, 3u)] uint size, //fp16 is not supported for now - [Values(0u)] uint rn, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm, - [Values] bool sub) + [Values(0u)] uint rn, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm, + [Values] bool sub) { var data = GenerateVectorSequence(0x1000); SetWorkingMemory(data); @@ -251,7 +251,7 @@ namespace Ryujinx.Tests.Cpu } opcode |= (uint)imm & 0xff; - SingleOpcode(opcode, r0: 0x2500); //correct + SingleOpcode(opcode, r0: 0x2500); CompareAgainstUnicorn(); } @@ -288,7 +288,7 @@ namespace Ryujinx.Tests.Cpu (V128 vec1, V128 vec2, _, _) = GenerateTestVectors(); - SingleOpcode(opcode, r0: 0x2500, v0: vec1, v1: vec2); //correct + SingleOpcode(opcode, r0: 0x2500, v0: vec1, v1: vec2); CompareAgainstUnicorn(); } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs index 6d650ac5d3..5624796550 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs @@ -16,9 +16,9 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VMOV.I
, #")] public void Movi_V([Range(0u, 10u)] uint variant, - [Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0x0u)] [Random(1u, 0xffu, RndCntImm)] uint imm, - [Values] bool q) + [Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0x0u)] [Random(1u, 0xffu, RndCntImm)] uint imm, + [Values] bool q) { uint[] variants = { @@ -54,17 +54,17 @@ namespace Ryujinx.Tests.Cpu opcode |= ((vd & 0x10) << 18); opcode |= ((vd & 0xf) << 12); - SingleOpcode(opcode); //correct + SingleOpcode(opcode); CompareAgainstUnicorn(); } [Test, Combinatorial, Description("VMOV.F , #")] public void Movi_S([Range(2u, 3u)] uint size, //fp16 is not supported for now - [Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm) + [Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm) { - uint opcode = 0xeeb00800; // invalid + uint opcode = 0xeeb00800; opcode |= (size & 3) << 8; opcode |= (imm & 0xf) | ((imm & 0xf0) << 12); @@ -79,7 +79,7 @@ namespace Ryujinx.Tests.Cpu opcode |= ((vd & 0xf) << 12); } - SingleOpcode(opcode); //correct + SingleOpcode(opcode); CompareAgainstUnicorn(); } @@ -106,14 +106,14 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VMOV. , ")] public void Mov_GP_Elem([Range(0u, 7u)] uint vn, - [Values(0u, 1u, 2u, 3u)] uint rt, - [Range(0u, 2u)] uint size, - [Range(0u, 7u)] uint index, - [Random(1)] uint valueRn, - [Random(1)] ulong valueVn1, - [Random(1)] ulong valueVn2, - [Values] bool op, - [Values] bool u) + [Values(0u, 1u, 2u, 3u)] uint rt, + [Range(0u, 2u)] uint size, + [Range(0u, 7u)] uint index, + [Random(1)] uint valueRn, + [Random(1)] ulong valueVn1, + [Random(1)] ulong valueVn2, + [Values] bool op, + [Values] bool u) { uint opcode = 0xee000b10; @@ -147,13 +147,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("(VMOV , , ), (VMOV , , )")] public void Mov_GP_D([Values(0u, 1u, 2u, 3u)] uint vm, - [Values(0u, 1u, 2u, 3u)] uint rt, - [Values(0u, 1u, 2u, 3u)] uint rt2, - [Random(RndCntImm)] uint valueRt1, - [Random(RndCntImm)] uint valueRt2, - [Random(RndCntImm)] ulong valueVn1, - [Random(RndCntImm)] ulong valueVn2, - [Values] bool op) + [Values(0u, 1u, 2u, 3u)] uint rt, + [Values(0u, 1u, 2u, 3u)] uint rt2, + [Random(RndCntImm)] uint valueRt1, + [Random(RndCntImm)] uint valueRt2, + [Random(RndCntImm)] ulong valueVn1, + [Random(RndCntImm)] ulong valueVn2, + [Values] bool op) { uint opcode = 0xec400b10; opcode |= (vm & 0x10) << 1; @@ -170,13 +170,13 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("(VMOV , , , ), (VMOV , , , )")] public void Mov_GP_2([Range(0u, 7u)] uint vm, - [Values(0u, 1u, 2u, 3u)] uint rt, - [Values(0u, 1u, 2u, 3u)] uint rt2, - [Random(RndCntImm)] uint valueRt1, - [Random(RndCntImm)] uint valueRt2, - [Random(RndCntImm)] ulong valueVn1, - [Random(RndCntImm)] ulong valueVn2, - [Values] bool op) + [Values(0u, 1u, 2u, 3u)] uint rt, + [Values(0u, 1u, 2u, 3u)] uint rt2, + [Random(RndCntImm)] uint valueRt1, + [Random(RndCntImm)] uint valueRt2, + [Random(RndCntImm)] ulong valueVn1, + [Random(RndCntImm)] ulong valueVn2, + [Values] bool op) { uint opcode = 0xec400a10; opcode |= (vm & 1) << 5; @@ -193,9 +193,9 @@ namespace Ryujinx.Tests.Cpu [Test, Combinatorial, Description("VTRN. , ")] public void Vtrn([Values(0u, 1u, 2u, 3u)] uint vm, - [Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0u, 1u, 2u)] uint size, - [Values] bool q) + [Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0u, 1u, 2u)] uint size, + [Values] bool q) { uint opcode = 0xf3b20080; if (vm == vd) return; //undefined @@ -216,16 +216,16 @@ namespace Ryujinx.Tests.Cpu V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); //correct + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); CompareAgainstUnicorn(); } [Test, Combinatorial, Description("VZIP. , ")] public void Vzip([Values(0u, 1u, 2u, 3u)] uint vm, - [Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0u, 1u, 2u)] uint size, - [Values] bool q) + [Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0u, 1u, 2u)] uint size, + [Values] bool q) { uint opcode = 0xf3b20180; if (vm == vd || (size == 2 && !q)) return; //undefined @@ -246,16 +246,16 @@ namespace Ryujinx.Tests.Cpu V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); //correct + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); CompareAgainstUnicorn(); } [Test, Combinatorial, Description("VUZP. , ")] public void Vuzp([Values(0u, 1u, 2u, 3u)] uint vm, - [Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0u, 1u, 2u)] uint size, - [Values] bool q) + [Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0u, 1u, 2u)] uint size, + [Values] bool q) { uint opcode = 0xf3b20100; if (vm == vd || (size == 2 && !q)) return; //undefined @@ -276,17 +276,17 @@ namespace Ryujinx.Tests.Cpu V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); //correct + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); CompareAgainstUnicorn(); } [Test, Combinatorial, Description("VTBL.8
, {list}, ")] public void Vtbl([Range(0u, 6u)] uint vm, //indices, include potentially invalid - [Range(4u, 12u)] uint vn, //selection - [Values(0u, 1u)] uint vd, //destinations - [Range(0u, 3u)] uint length, - [Values] bool x) + [Range(4u, 12u)] uint vn, //selection + [Values(0u, 1u)] uint vd, //destinations + [Range(0u, 3u)] uint length, + [Values] bool x) { uint opcode = 0xf3b00800; if (vn + length > 31) return; //undefined @@ -322,7 +322,7 @@ namespace Ryujinx.Tests.Cpu V128 v0 = new V128(b0); V128 v1 = new V128(b1); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5); //correct + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5); CompareAgainstUnicorn(); } @@ -355,19 +355,19 @@ namespace Ryujinx.Tests.Cpu V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); //correct + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); CompareAgainstUnicorn(); } [Test, Pairwise, Description("VDUP , ")] public void Vdup_GP([Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0u, 1u, 2u, 3u)] uint rt, - [Values(0u, 1u, 2u)] uint size, - [Random(RndCntImm)] uint valueRn, - [Random(RndCntImm)] ulong valueVn1, - [Random(RndCntImm)] ulong valueVn2, - [Values] bool q) + [Values(0u, 1u, 2u, 3u)] uint rt, + [Values(0u, 1u, 2u)] uint size, + [Random(RndCntImm)] uint valueRn, + [Random(RndCntImm)] ulong valueVn1, + [Random(RndCntImm)] ulong valueVn2, + [Values] bool q) { uint opcode = 0xee800b10; @@ -393,12 +393,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VDUP. , ")] public void Vdup_S([Values(0u, 1u, 2u, 3u)] uint vd, - [Values(0u, 1u, 2u, 3u)] uint vm, - [Values(0u, 1u, 2u)] uint size, - [Range(0u, 7u)] uint index, - [Random(RndCntImm)] ulong valueVn1, - [Random(RndCntImm)] ulong valueVn2, - [Values] bool q) + [Values(0u, 1u, 2u, 3u)] uint vm, + [Values(0u, 1u, 2u)] uint size, + [Range(0u, 7u)] uint index, + [Random(RndCntImm)] ulong valueVn1, + [Random(RndCntImm)] ulong valueVn2, + [Values] bool q) { uint opcode = 0xf3b00c00; diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index f0560090d7..5d2429a819 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -210,12 +210,12 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VADD.f32 V0, V0, V0")] public void Vadd_f32([Values(0u)] uint rd, - [Values(1u, 0u)] uint rn, - [Values(2u, 0u)] uint rm, - [ValueSource("_2S_F_")] [Random(RndCnt)] ulong z, - [ValueSource("_2S_F_")] [Random(RndCnt)] ulong a, - [ValueSource("_2S_F_")] [Random(RndCnt)] ulong b, - [Values] bool q) + [Values(1u, 0u)] uint rn, + [Values(2u, 0u)] uint rm, + [ValueSource("_2S_F_")] [Random(RndCnt)] ulong z, + [ValueSource("_2S_F_")] [Random(RndCnt)] ulong a, + [ValueSource("_2S_F_")] [Random(RndCnt)] ulong b, + [Values] bool q) { uint opcode = 0xf2000d00; // VADD.f32 D0, D0, D0 if (q) @@ -242,9 +242,9 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VCMP.f Vd, Vm")] public void Vcmp([Values(2u, 3u)] uint size, - [ValueSource("_1S_F_")] ulong a, - [ValueSource("_1S_F_")] ulong b, - [Values] bool e) + [ValueSource("_1S_F_")] ulong a, + [ValueSource("_1S_F_")] ulong b, + [Values] bool e) { uint opcode = 0xeeb40840; uint rm = 1; @@ -259,6 +259,7 @@ namespace Ryujinx.Tests.Cpu opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5); opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22); } + opcode |= ((size & 3) << 8); if (e) opcode |= 1 << 7; @@ -279,14 +280,14 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("VSHL. {}, , ")] public void Vshl([Values(0u)] uint rd, - [Values(1u, 0u)] uint rn, - [Values(2u, 0u)] uint rm, - [Values(0u, 1u, 2u, 3u)] uint size, - [Random(RndCnt)] ulong z, - [Random(RndCnt)] ulong a, - [Random(RndCnt)] ulong b, - [Values] bool q, - [Values] bool u) + [Values(1u, 0u)] uint rn, + [Values(2u, 0u)] uint rm, + [Values(0u, 1u, 2u, 3u)] uint size, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool q, + [Values] bool u) { uint opcode = 0xf2000400; if (q) @@ -317,22 +318,12 @@ namespace Ryujinx.Tests.Cpu [Range(0u, 7u)] uint rn, [Range(0u, 7u)] uint rm) { - uint opcode = 0xf3000d00; // VADD.f32 D0, D0, D0 - /* - if (q) - { - rm <<= 0x1e; - rn <<= 0x1e; - rd <<= 0x1e; - } - */ + uint opcode = 0xf3000d00; opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3); - //if (q) opcode |= 1 << 6; - var rnd = TestContext.CurrentContext.Random; V128 v0 = new V128(rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue)); V128 v1 = new V128(rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue), rnd.NextFloat(int.MinValue, int.MaxValue));