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Ensure that Spill and Fill don't load or store any more than necessary

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This commit is contained in:
gdkchan 2019-08-08 12:00:10 -03:00
parent 1dcb921904
commit 7f59d50cd3
1 changed files with 32 additions and 36 deletions
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68
ARMeilleure/CodeGen/X86/CodeGenerator.cs
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@ -771,14 +771,7 @@ namespace ARMeilleure.CodeGen.X86
MemoryOperand memOp = new MemoryOperand(dest.Type, rsp, null, Multiplier.x1, offs);
if (dest.Type.IsInteger())
{
context.Assembler.Mov(dest, memOp, dest.Type);
}
else
{
context.Assembler.Movdqu(dest, memOp);
}
GenerateLoad(context, memOp, dest);
}
private static void GenerateLoad(CodeGenContext context, Operation operation)
@ -786,16 +779,7 @@ namespace ARMeilleure.CodeGen.X86
Operand value = operation.Destination;
Operand address = Memory(operation.GetSource(0), value.Type);
switch (value.Type)
{
case OperandType.I32: context.Assembler.Mov (value, address, OperandType.I32); break;
case OperandType.I64: context.Assembler.Mov (value, address, OperandType.I64); break;
case OperandType.FP32: context.Assembler.Movd (value, address); break;
case OperandType.FP64: context.Assembler.Movq (value, address); break;
case OperandType.V128: context.Assembler.Movdqu(value, address); break;
default: Debug.Assert(false); break;
}
GenerateLoad(context, address, value);
}
private static void GenerateLoad16(CodeGenContext context, Operation operation)
@ -986,14 +970,7 @@ namespace ARMeilleure.CodeGen.X86
MemoryOperand memOp = new MemoryOperand(source.Type, rsp, null, Multiplier.x1, offs);
if (source.GetRegister().Type == RegisterType.Integer)
{
context.Assembler.Mov(memOp, source, source.Type);
}
else
{
context.Assembler.Movdqu(memOp, source);
}
GenerateStore(context, memOp, source);
}
private static void GenerateStackAlloc(CodeGenContext context, Operation operation)
@ -1017,16 +994,7 @@ namespace ARMeilleure.CodeGen.X86
Operand value = operation.GetSource(1);
Operand address = Memory(operation.GetSource(0), value.Type);
switch (value.Type)
{
case OperandType.I32: context.Assembler.Mov (address, value, OperandType.I32); break;
case OperandType.I64: context.Assembler.Mov (address, value, OperandType.I64); break;
case OperandType.FP32: context.Assembler.Movd (address, value); break;
case OperandType.FP64: context.Assembler.Movq (address, value); break;
case OperandType.V128: context.Assembler.Movdqu(address, value); break;
default: Debug.Assert(false); break;
}
GenerateStore(context, address, value);
}
private static void GenerateStore16(CodeGenContext context, Operation operation)
@ -1455,6 +1423,34 @@ namespace ARMeilleure.CodeGen.X86
context.Assembler.Movzx8(dest, source, OperandType.I32);
}
private static void GenerateLoad(CodeGenContext context, Operand address, Operand value)
{
switch (value.Type)
{
case OperandType.I32: context.Assembler.Mov (value, address, OperandType.I32); break;
case OperandType.I64: context.Assembler.Mov (value, address, OperandType.I64); break;
case OperandType.FP32: context.Assembler.Movd (value, address); break;
case OperandType.FP64: context.Assembler.Movq (value, address); break;
case OperandType.V128: context.Assembler.Movdqu(value, address); break;
default: Debug.Assert(false); break;
}
}
private static void GenerateStore(CodeGenContext context, Operand address, Operand value)
{
switch (value.Type)
{
case OperandType.I32: context.Assembler.Mov (address, value, OperandType.I32); break;
case OperandType.I64: context.Assembler.Mov (address, value, OperandType.I64); break;
case OperandType.FP32: context.Assembler.Movd (address, value); break;
case OperandType.FP64: context.Assembler.Movq (address, value); break;
case OperandType.V128: context.Assembler.Movdqu(address, value); break;
default: Debug.Assert(false); break;
}
}
private static void GenerateZeroUpper64(CodeGenContext context, Operand dest, Operand source)
{
context.Assembler.Movq(dest, source);