From 82b9cfc45cc746f8280395917bb1e0590f98587f Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 17 Nov 2018 16:21:01 +0100
Subject: [PATCH] Create CpuTestSimdExt.cs

---
 Ryujinx.Tests/Cpu/CpuTestSimdExt.cs | 73 +++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 Ryujinx.Tests/Cpu/CpuTestSimdExt.cs

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs b/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs
new file mode 100644
index 0000000000..f232989f77
--- /dev/null
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs
@@ -0,0 +1,73 @@
+#define SimdExt
+
+using NUnit.Framework;
+
+using System.Runtime.Intrinsics;
+
+namespace Ryujinx.Tests.Cpu
+{
+    [Category("SimdExt")]
+    public sealed class CpuTestSimdExt : CpuTest
+    {
+#if SimdExt
+
+#region "ValueSource"
+        private static ulong[] _8B_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+        }
+#endregion
+
+        private const int RndCnt = 2;
+
+        [Test, Pairwise, Description("EXT <Vd>.8B, <Vn>.8B, <Vm>.8B, #<index>")]
+        public void Ext_V_8B([Values(0u)]     uint rd,
+                             [Values(1u, 0u)] uint rn,
+                             [Values(2u, 0u)] uint rm,
+                             [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
+                             [ValueSource("_8B_")] [Random(RndCnt)] ulong a,
+                             [ValueSource("_8B_")] [Random(RndCnt)] ulong b,
+                             [Range(0u, 7u)] uint index)
+        {
+            uint imm4 = index & 0x7u;
+
+            uint opcode = 0x2E000000; // EXT V0.8B, V0.8B, V0.8B, #0
+            opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcode |= (imm4 << 11);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0(a);
+            Vector128<float> v2 = MakeVectorE0(b);
+
+            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("EXT <Vd>.16B, <Vn>.16B, <Vm>.16B, #<index>")]
+        public void Ext_V_16B([Values(0u)]     uint rd,
+                              [Values(1u, 0u)] uint rn,
+                              [Values(2u, 0u)] uint rm,
+                              [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
+                              [ValueSource("_8B_")] [Random(RndCnt)] ulong a,
+                              [ValueSource("_8B_")] [Random(RndCnt)] ulong b,
+                              [Range(0u, 15u)] uint index)
+        {
+            uint imm4 = index & 0xFu;
+
+            uint opcode = 0x6E000000; // EXT V0.16B, V0.16B, V0.16B, #0
+            opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+            opcode |= (imm4 << 11);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+            Vector128<float> v1 = MakeVectorE0E1(a, a);
+            Vector128<float> v2 = MakeVectorE0E1(b, b);
+
+            SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
+
+            CompareAgainstUnicorn();
+        }
+#endif
+    }
+}