opt_p2
This commit is contained in:
LDj3SNuD
parent
5c581ac24b
commit
844954abb7
6 changed files with 110 additions and 98 deletions
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@ -321,32 +321,61 @@ namespace ARMeilleure.Instructions
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if (op.RegisterSize == RegisterSize.Int32)
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{
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d = context.Call(new _U32_U32(SoftFallback.ReverseBytes16_32), n);
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d = EmitReverseBytes16_32Op(context, n);
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}
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else
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{
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d = context.Call(new _U64_U64(SoftFallback.ReverseBytes16_64), n);
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d = EmitReverseBytes16_64Op(context, n);
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}
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SetAluDOrZR(context, d);
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}
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private static Operand EmitReverseBytes16_32Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I32);
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Operand val = context.ZeroExtend32 (OperandType.I64, op);
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val = EmitReverseBytes16_64Op(context, val);
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return context.ConvertI64ToI32(val);
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}
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private static Operand EmitReverseBytes16_64Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I64);
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return context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xff00ff00ff00ff00ul)), Const(8)),
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context.ShiftLeft (context.BitwiseAnd(op, Const(0x00ff00ff00ff00fful)), Const(8)));
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}
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public static void Rev32(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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Operand d;
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if (op.RegisterSize == RegisterSize.Int32)
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{
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SetAluDOrZR(context, context.ByteSwap(n));
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d = context.ByteSwap(n);
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}
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else
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{
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Operand d = context.Call(new _U64_U64(SoftFallback.ReverseBytes32_64), n);
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SetAluDOrZR(context, d);
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d = EmitReverseBytes32_64Op(context, n);
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}
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SetAluDOrZR(context, d);
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}
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private static Operand EmitReverseBytes32_64Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I64);
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Operand val = EmitReverseBytes16_64Op(context, op);
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return context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)),
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context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16)));
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}
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public static void Rev64(ArmEmitterContext context)
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@ -671,7 +671,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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else /* if (sizeF == 1) */
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{
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@ -679,7 +679,7 @@ namespace ARMeilleure.Instructions
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res = context.AddIntrinsic(Intrinsic.X86Addpd, d, res);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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@ -717,7 +717,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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else /* if (sizeF == 1) */
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{
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@ -728,7 +728,7 @@ namespace ARMeilleure.Instructions
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res = context.AddIntrinsic(Intrinsic.X86Mulpd, n, res);
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res = context.AddIntrinsic(Intrinsic.X86Addpd, d, res);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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@ -771,7 +771,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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else /* if (sizeF == 1) */
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{
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@ -779,7 +779,7 @@ namespace ARMeilleure.Instructions
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res = context.AddIntrinsic(Intrinsic.X86Subpd, d, res);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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@ -817,7 +817,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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else /* if (sizeF == 1) */
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{
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@ -828,7 +828,7 @@ namespace ARMeilleure.Instructions
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res = context.AddIntrinsic(Intrinsic.X86Mulpd, n, res);
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res = context.AddIntrinsic(Intrinsic.X86Subpd, d, res);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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}
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else
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@ -3055,7 +3055,9 @@ namespace ARMeilleure.Instructions
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int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
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Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
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Operand d = GetVec(op.Rd);
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Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
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long roundConst = 1L << (eSize - 1);
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@ -3076,7 +3078,7 @@ namespace ARMeilleure.Instructions
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res = EmitVectorInsert(context, res, de, part + index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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public static void EmitScalarRoundOpF(ArmEmitterContext context, FPRoundingMode roundMode)
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@ -1034,9 +1034,7 @@ namespace ARMeilleure.Instructions
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Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
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Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
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Operand res = context.AddIntrinsic(inst[op.Size], left, right);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
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}
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else if (op.Size < 3)
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{
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@ -1048,18 +1046,14 @@ namespace ARMeilleure.Instructions
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Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
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Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
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Operand res = context.AddIntrinsic(inst[op.Size], left, right);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
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}
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else
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{
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Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
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Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
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Operand res = context.AddIntrinsic(inst[3], left, right);
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context.Copy(GetVec(op.Rd), res);
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right));
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}
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}
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@ -1303,8 +1297,7 @@ namespace ARMeilleure.Instructions
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if (op.Size <= 2)
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{
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Operand temp = add ? context.Add (ne, me)
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: context.Subtract(ne, me);
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Operand temp = add ? context.Add(ne, me) : context.Subtract(ne, me);
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de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
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}
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@ -1388,7 +1381,9 @@ namespace ARMeilleure.Instructions
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int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0;
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Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
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Operand d = GetVec(op.Rd);
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Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
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for (int index = 0; index < elems; index++)
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{
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@ -1399,7 +1394,7 @@ namespace ARMeilleure.Instructions
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res = EmitVectorInsert(context, res, temp, part + index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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// TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
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@ -1,6 +1,7 @@
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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@ -107,7 +108,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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else
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{
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@ -158,7 +159,7 @@ namespace ARMeilleure.Instructions
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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else
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{
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@ -292,11 +293,7 @@ namespace ARMeilleure.Instructions
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, index, 0);
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ne = context.ConvertI64ToI32(ne);
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Operand de = context.Call(new _U32_U32(SoftFallback.ReverseBits8), ne);
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de = context.ZeroExtend32(OperandType.I64, de);
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Operand de = EmitReverseBits8Op(context, ne);
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res = EmitVectorInsert(context, res, de, index, 0);
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}
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@ -304,6 +301,20 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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}
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private static Operand EmitReverseBits8Op(ArmEmitterContext context, Operand op)
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{
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Debug.Assert(op.Type == OperandType.I64);
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Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaul)), Const(1)),
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context.ShiftLeft (context.BitwiseAnd(op, Const(0x55ul)), Const(1)));
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val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccul)), Const(2)),
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context.ShiftLeft (context.BitwiseAnd(val, Const(0x33ul)), Const(2)));
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return context.BitwiseOr(context.ShiftRightUI(val, Const(4)),
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context.ShiftLeft (context.BitwiseAnd(val, Const(0x0ful)), Const(4)));
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}
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public static void Rev16_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSsse3)
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@ -4,6 +4,7 @@ using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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@ -35,7 +36,7 @@ namespace ARMeilleure.Instructions
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand dLow = context.AddIntrinsic(Intrinsic.X86Movlhps, d, context.VectorZero());
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Operand dLow = context.VectorZeroUpper64(d);
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Operand mask = null;
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@ -150,7 +151,7 @@ namespace ARMeilleure.Instructions
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand dLow = context.AddIntrinsic(Intrinsic.X86Movlhps, d, context.VectorZero());
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Operand dLow = context.VectorZeroUpper64(d);
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Intrinsic srlInst = X86PsrlInstruction[op.Size + 1];
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@ -695,9 +696,9 @@ namespace ARMeilleure.Instructions
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
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Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
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Operand me = EmitVectorExtractSx(context, op.Rm, index << op.Size, 0);
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Operand e = context.Call(new _U64_U64_U64_Bool_S32(SoftFallback.UnsignedShlReg), ne, me, Const(0), Const(op.Size));
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Operand e = EmitUnsignedShlRegOp(context, ne, context.ConvertI64ToI32(me), op.Size);
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res = EmitVectorInsert(context, res, e, index, op.Size);
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}
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@ -872,9 +873,7 @@ namespace ARMeilleure.Instructions
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e = context.Add(e, Const(roundConst));
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}
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e = signed
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? context.ShiftRightSI(e, Const(shift))
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: context.ShiftRightUI(e, Const(shift));
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e = signed ? context.ShiftRightSI(e, Const(shift)) : context.ShiftRightUI(e, Const(shift));
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}
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else /* if (op.Size == 3) */
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{
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@ -894,6 +893,28 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), res);
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}
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private static Operand EmitUnsignedShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size)
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{
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Debug.Assert(op.Type == OperandType.I64);
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Debug.Assert(shiftLsB.Type == OperandType.I32);
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Debug.Assert((uint)size < 4u);
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Operand negShiftLsB = context.Negate(shiftLsB);
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Operand isPositive = context.ICompareGreaterOrEqual(shiftLsB, Const(0));
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Operand shl = context.ShiftLeft (op, shiftLsB);
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Operand shr = context.ShiftRightUI(op, negShiftLsB);
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Operand res = context.ConditionalSelect(isPositive, shl, shr);
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Operand isOutOfRange = context.BitwiseOr(
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context.ICompareGreaterOrEqual(shiftLsB, Const(8 << size)),
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context.ICompareGreaterOrEqual(negShiftLsB, Const(8 << size)));
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return context.ConditionalSelect(isOutOfRange, Const(0UL), res);
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}
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private static void EmitVectorShrImmNarrowOpZx(ArmEmitterContext context, bool round)
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{
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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@ -906,7 +927,9 @@ namespace ARMeilleure.Instructions
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int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
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Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
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Operand d = GetVec(op.Rd);
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Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
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for (int index = 0; index < elems; index++)
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{
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@ -922,7 +945,7 @@ namespace ARMeilleure.Instructions
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res = EmitVectorInsert(context, res, e, part + index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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[Flags]
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@ -965,7 +988,9 @@ namespace ARMeilleure.Instructions
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int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0;
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Operand res = part == 0 ? context.VectorZero() : context.Copy(GetVec(op.Rd));
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Operand d = GetVec(op.Rd);
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Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
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for (int index = 0; index < elems; index++)
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{
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@ -978,9 +1003,7 @@ namespace ARMeilleure.Instructions
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e = context.Add(e, Const(roundConst));
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}
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e = signedSrc
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? context.ShiftRightSI(e, Const(shift))
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: context.ShiftRightUI(e, Const(shift));
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e = signedSrc ? context.ShiftRightSI(e, Const(shift)) : context.ShiftRightUI(e, Const(shift));
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}
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else /* if (op.Size == 2 && round) */
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{
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@ -992,7 +1015,7 @@ namespace ARMeilleure.Instructions
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res = EmitVectorInsert(context, res, e, part + index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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context.Copy(d, res);
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}
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// dst64 = (Int(src64, signed) + roundConst) >> shift;
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@ -1240,53 +1240,5 @@ namespace ARMeilleure.Instructions
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: (uint)(value >> 32);
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}
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#endregion
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#region "Reverse"
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public static uint ReverseBits8(uint value)
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{
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value = ((value & 0xaa) >> 1) | ((value & 0x55) << 1);
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value = ((value & 0xcc) >> 2) | ((value & 0x33) << 2);
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return (value >> 4) | ((value & 0x0f) << 4);
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}
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|
||||
public static uint ReverseBytes16_32(uint value) => (uint)ReverseBytes16_64(value);
|
||||
|
||||
public static ulong ReverseBytes16_64(ulong value) => ReverseBytes(value, RevSize.Rev16);
|
||||
public static ulong ReverseBytes32_64(ulong value) => ReverseBytes(value, RevSize.Rev32);
|
||||
|
||||
private enum RevSize
|
||||
{
|
||||
Rev16,
|
||||
Rev32,
|
||||
Rev64
|
||||
}
|
||||
|
||||
private static ulong ReverseBytes(ulong value, RevSize size)
|
||||
{
|
||||
value = ((value & 0xff00ff00ff00ff00) >> 8) | ((value & 0x00ff00ff00ff00ff) << 8);
|
||||
|
||||
if (size == RevSize.Rev16)
|
||||
{
|
||||
return value;
|
||||
}
|
||||
|
||||
value = ((value & 0xffff0000ffff0000) >> 16) | ((value & 0x0000ffff0000ffff) << 16);
|
||||
|
||||
if (size == RevSize.Rev32)
|
||||
{
|
||||
return value;
|
||||
}
|
||||
|
||||
value = ((value & 0xffffffff00000000) >> 32) | ((value & 0x00000000ffffffff) << 32);
|
||||
|
||||
if (size == RevSize.Rev64)
|
||||
{
|
||||
return value;
|
||||
}
|
||||
|
||||
throw new ArgumentException(nameof(size));
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue