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LDj3SNuD 2019-03-12 19:04:18 +01:00 • committed by GitHub
commit 8d65ac0fe6
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1 changed files with 14 additions and 14 deletions
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28
ChocolArm64/Instructions/InstEmitSimdLogical.cs
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@ -30,12 +30,12 @@ namespace ChocolArm64.Instructions
{ {
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] typesAndNot = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) }; Type[] typesAnt = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAnt));
context.EmitStvec(op.Rd); context.EmitStvec(op.Rd);
@ -79,18 +79,18 @@ namespace ChocolArm64.Instructions
if (Optimizations.UseSse2) if (Optimizations.UseSse2)
{ {
Type[] typesXorAndNot = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) }; Type[] typesXorAnd = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
string nameAndNot = notRm ? nameof(Sse2.AndNot) : nameof(Sse2.And); string nameAnd = notRm ? nameof(Sse2.AndNot) : nameof(Sse2.And);
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rd); context.EmitLdvec(op.Rd);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAndNot)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAnd));
context.EmitCall(typeof(Sse2).GetMethod(nameAndNot, typesXorAndNot)); context.EmitCall(typeof(Sse2).GetMethod(nameAnd, typesXorAnd));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAndNot)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAnd));
context.EmitStvec(op.Rd); context.EmitStvec(op.Rd);
@ -193,15 +193,15 @@ namespace ChocolArm64.Instructions
{ {
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
Type[] typesSav = new Type[] { typeof(byte) }; Type[] typesSav = new Type[] { typeof(byte) };
Type[] typesAndNot = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) }; Type[] typesAnt = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
context.EmitLdc_I4(byte.MaxValue); context.EmitLdc_I4(byte.MaxValue);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAnt));
context.EmitStvec(op.Rd); context.EmitStvec(op.Rd);
@ -222,8 +222,8 @@ namespace ChocolArm64.Instructions
{ {
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp; OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
Type[] typesSav = new Type[] { typeof(byte) }; Type[] typesSav = new Type[] { typeof(byte) };
Type[] typesAndNotOr = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) }; Type[] typesAntOr = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
@ -231,8 +231,8 @@ namespace ChocolArm64.Instructions
context.EmitLdc_I4(byte.MaxValue); context.EmitLdc_I4(byte.MaxValue);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNotOr)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAntOr));
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesAndNotOr)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesAntOr));
context.EmitStvec(op.Rd); context.EmitStvec(op.Rd);