From 8f0013986c3f0c9bc54e42a7622bedd6f86687cf Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Sun, 24 Jun 2018 03:18:18 +0200 Subject: [PATCH] Add files via upload --- Ryujinx.Tests/Cpu/CpuTest.cs | 33 +- Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 22 +- Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs | 376 +++++++++++++++++++++ Ryujinx.Tests/Cpu/CpuTestSimdMove.cs | 62 ++-- 4 files changed, 448 insertions(+), 45 deletions(-) create mode 100644 Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs index e2442ee492..2af50c6c89 100644 --- a/Ryujinx.Tests/Cpu/CpuTest.cs +++ b/Ryujinx.Tests/Cpu/CpuTest.cs @@ -113,6 +113,22 @@ namespace Ryujinx.Tests.Cpu return GetThreadState(); } + protected static Vector128 MakeVectorE0(double A0) + { + return Sse.StaticCast(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(A0))); + } + + protected static Vector128 MakeVectorE0E1(double A0, double A1) + { + return Sse.StaticCast(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(A1), + BitConverter.DoubleToInt64Bits(A0))); + } + + protected static Vector128 MakeVectorE1(double A1) + { + return Sse.StaticCast(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(A1), 0)); + } + protected static double VectorExtractDouble(Vector128 Vector, byte Index) { long Value = Sse41.Extract(Sse.StaticCast(Vector), Index); @@ -120,24 +136,19 @@ namespace Ryujinx.Tests.Cpu return BitConverter.Int64BitsToDouble(Value); } - protected static Vector128 MakeVectorE0(double A) + protected static Vector128 MakeVectorE0(ulong A0) { - return Sse.StaticCast(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(A))); + return Sse.StaticCast(Sse2.SetVector128(0, A0)); } - protected static Vector128 MakeVectorE0(ulong A) + protected static Vector128 MakeVectorE0E1(ulong A0, ulong A1) { - return Sse.StaticCast(Sse2.SetVector128(0, A)); + return Sse.StaticCast(Sse2.SetVector128(A1, A0)); } - protected static Vector128 MakeVectorE0E1(ulong A, ulong B) + protected static Vector128 MakeVectorE1(ulong A1) { - return Sse.StaticCast(Sse2.SetVector128(B, A)); - } - - protected static Vector128 MakeVectorE1(ulong B) - { - return Sse.StaticCast(Sse2.SetVector128(B, 0)); + return Sse.StaticCast(Sse2.SetVector128(A1, 0)); } protected static ulong GetVectorE0(Vector128 Vector) diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index d04eca7b55..98be2fc5be 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -176,10 +176,13 @@ namespace Ryujinx.Tests.Cpu { AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: Sse.SetAllVector128(A)); - Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A)); - Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A)); - Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A)); - Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A)); + Assert.Multiple(() => + { + Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A)); + Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A)); + Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A)); + Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A)); + }); } [Test, Description("FRECPS D0, D1, D2")] @@ -199,10 +202,13 @@ namespace Ryujinx.Tests.Cpu V2: Sse.SetAllVector128(A), V0: Sse.SetAllVector128(B)); - Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B))); - Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B))); - Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B))); - Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B))); + Assert.Multiple(() => + { + Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B))); + Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B))); + Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B))); + Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B))); + }); } [TestCase(0x3FE66666u, false, 0x40000000u)] diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs new file mode 100644 index 0000000000..deb2021673 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs @@ -0,0 +1,376 @@ +using ChocolArm64.State; + +using NUnit.Framework; + +using System; +using System.Runtime.Intrinsics; +using System.Runtime.Intrinsics.X86; + +namespace Ryujinx.Tests.Cpu +{ + public class CpuTestSimdCmp : CpuTest + { +#region "ValueSource" + private static float[] _floats_() + { + return new float[] { float.NegativeInfinity, float.MinValue, -1f, -0f, + +0f, +1f, float.MaxValue, float.PositiveInfinity }; + } + + private static double[] _doubles_() + { + return new double[] { double.NegativeInfinity, double.MinValue, -1d, -0d, + +0d, +1d, double.MaxValue, double.PositiveInfinity }; + } +#endregion + + [Test, Description("FCMEQ D0, D1, D2 | FCMGE D0, D1, D2 | FCMGT D0, D1, D2")] + public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(8)] double A, + [ValueSource("_doubles_")] [Random(8)] double B, + [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT + { + uint Opcode = 0x5E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble())); + Vector128 V1 = Sse.StaticCast(Sse2.SetScalarVector128(A)); + Vector128 V2 = Sse.StaticCast(Sse2.SetScalarVector128(B)); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + switch (EU) + { + case 0: Exp = (A == B ? Ones : Zeros); break; + case 1: Exp = (A >= B ? Ones : Zeros); break; + case 3: Exp = (A > B ? Ones : Zeros); break; + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero); + }); + } + + [Test, Description("FCMEQ S0, S1, S2 | FCMGE S0, S1, S2 | FCMGT S0, S1, S2")] + public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(8)] float A, + [ValueSource("_floats_")] [Random(8)] float B, + [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT + { + uint Opcode = 0x5E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); + Vector128 V1 = Sse.SetScalarVector128(A); + Vector128 V2 = Sse.SetScalarVector128(B); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00}; + + switch (EU) + { + case 0: Exp = (A == B ? Ones : Zeros); break; + case 1: Exp = (A >= B ? Ones : Zeros); break; + case 3: Exp = (A > B ? Ones : Zeros); break; + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)1), Is.Zero); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); + }); + } + + [Test, Description("FCMEQ V0.2D, V1.2D, V2.2D | FCMGE V0.2D, V1.2D, V2.2D | FCMGT V0.2D, V1.2D, V2.2D")] + public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(8)] double A, + [ValueSource("_doubles_")] [Random(8)] double B, + [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT + { + uint Opcode = 0x4E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V1 = Sse.StaticCast(Sse2.SetAllVector128(A)); + Vector128 V2 = Sse.StaticCast(Sse2.SetAllVector128(B)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + switch (EU) + { + case 0: Exp = (A == B ? Ones : Zeros); break; + case 1: Exp = (A >= B ? Ones : Zeros); break; + case 3: Exp = (A > B ? Ones : Zeros); break; + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); + }); + } + + [Test, Description("FCMEQ V0.2S, V1.2S, V2.2S | FCMGE V0.2S, V1.2S, V2.2S | FCMGT V0.2S, V1.2S, V2.2S")] + public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(8)] float A, + [ValueSource("_floats_")] [Random(8)] float B, + [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT + { + uint Opcode = 0x0E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); + Vector128 V1 = Sse.SetVector128(0, 0, A, A); + Vector128 V2 = Sse.SetVector128(0, 0, B, B); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00}; + + switch (EU) + { + case 0: Exp = (A == B ? Ones : Zeros); break; + case 1: Exp = (A >= B ? Ones : Zeros); break; + case 3: Exp = (A > B ? Ones : Zeros); break; + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); + }); + } + + [Test, Description("FCMEQ V0.4S, V1.4S, V2.4S | FCMGE V0.4S, V1.4S, V2.4S | FCMGT V0.4S, V1.4S, V2.4S")] + public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(8)] float A, + [ValueSource("_floats_")] [Random(8)] float B, + [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT + { + uint Opcode = 0x4E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V1 = Sse.SetAllVector128(A); + Vector128 V2 = Sse.SetAllVector128(B); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00}; + + switch (EU) + { + case 0: Exp = (A == B ? Ones : Zeros); break; + case 1: Exp = (A >= B ? Ones : Zeros); break; + case 3: Exp = (A > B ? Ones : Zeros); break; + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp)); + }); + } + + + [Test, Description("FCMGT D0, D1, #0.0 | FCMGE D0, D1, #0.0 | FCMEQ D0, D1, #0.0 | FCMLE D0, D1, #0.0 | FCMLT D0, D1, #0.0")] + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(8)] double A, + [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE + [Values(0u, 1u)] uint bit13) // "LT" + { + uint Opcode = 0x5EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble())); + Vector128 V1 = Sse.StaticCast(Sse2.SetScalarVector128(A)); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + double Zero = +0d; + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + if (bit13 == 0) + { + switch (opU) + { + case 0: Exp = (A > Zero ? Ones : Zeros); break; + case 1: Exp = (A >= Zero ? Ones : Zeros); break; + case 2: Exp = (A == Zero ? Ones : Zeros); break; + case 3: Exp = (Zero >= A ? Ones : Zeros); break; + } + } + else + { + Exp = (Zero > A ? Ones : Zeros); + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero); + }); + } + + [Test, Description("FCMGT S0, S1, #0.0 | FCMGE S0, S1, #0.0 | FCMEQ S0, S1, #0.0 | FCMLE S0, S1, #0.0 | FCMLT S0, S1, #0.0")] + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(8)] float A, + [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE + [Values(0u, 1u)] uint bit13) // "LT" + { + uint Opcode = 0x5EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); + Vector128 V1 = Sse.SetScalarVector128(A); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + double Zero = +0f; + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00}; + + if (bit13 == 0) + { + switch (opU) + { + case 0: Exp = (A > Zero ? Ones : Zeros); break; + case 1: Exp = (A >= Zero ? Ones : Zeros); break; + case 2: Exp = (A == Zero ? Ones : Zeros); break; + case 3: Exp = (Zero >= A ? Ones : Zeros); break; + } + } + else + { + Exp = (Zero > A ? Ones : Zeros); + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)1), Is.Zero); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); + }); + } + + [Test, Description("FCMGT V0.2D, V1.2D, #0.0 | FCMGE V0.2D, V1.2D, #0.0 | FCMEQ V0.2D, V1.2D, #0.0 | FCMLE V0.2D, V1.2D, #0.0 | FCMLT V0.2D, V1.2D, #0.0")] + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(8)] double A, + [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE + [Values(0u, 1u)] uint bit13) // "LT" + { + uint Opcode = 0x4EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V1 = Sse.StaticCast(Sse2.SetAllVector128(A)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); + + double Zero = +0d; + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + if (bit13 == 0) + { + switch (opU) + { + case 0: Exp = (A > Zero ? Ones : Zeros); break; + case 1: Exp = (A >= Zero ? Ones : Zeros); break; + case 2: Exp = (A == Zero ? Ones : Zeros); break; + case 3: Exp = (Zero >= A ? Ones : Zeros); break; + } + } + else + { + Exp = (Zero > A ? Ones : Zeros); + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); + }); + } + + [Test, Description("FCMGT V0.2S, V1.2S, #0.0 | FCMGE V0.2S, V1.2S, #0.0 | FCMEQ V0.2S, V1.2S, #0.0 | FCMLE V0.2S, V1.2S, #0.0 | FCMLT V0.2S, V1.2S, #0.0")] + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(8)] float A, + [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE + [Values(0u, 1u)] uint bit13) // "LT" + { + uint Opcode = 0x0EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); + Vector128 V1 = Sse.SetVector128(0, 0, A, A); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + double Zero = +0f; + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00}; + + if (bit13 == 0) + { + switch (opU) + { + case 0: Exp = (A > Zero ? Ones : Zeros); break; + case 1: Exp = (A >= Zero ? Ones : Zeros); break; + case 2: Exp = (A == Zero ? Ones : Zeros); break; + case 3: Exp = (Zero >= A ? Ones : Zeros); break; + } + } + else + { + Exp = (Zero > A ? Ones : Zeros); + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); + Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); + }); + } + + [Test, Description("FCMGT V0.4S, V1.4S, #0.0 | FCMGE V0.4S, V1.4S, #0.0 | FCMEQ V0.4S, V1.4S, #0.0 | FCMLE V0.4S, V1.4S, #0.0 | FCMLT V0.4S, V1.4S, #0.0")] + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(8)] float A, + [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE + [Values(0u, 1u)] uint bit13) // "LT" + { + uint Opcode = 0x4EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V1 = Sse.SetAllVector128(A); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); + + double Zero = +0f; + byte[] Exp = default(byte[]); + byte[] Ones = new byte[] {0xFF, 0xFF, 0xFF, 0xFF}; + byte[] Zeros = new byte[] {0x00, 0x00, 0x00, 0x00}; + + if (bit13 == 0) + { + switch (opU) + { + case 0: Exp = (A > Zero ? Ones : Zeros); break; + case 1: Exp = (A >= Zero ? Ones : Zeros); break; + case 2: Exp = (A == Zero ? Ones : Zeros); break; + case 3: Exp = (Zero >= A ? Ones : Zeros); break; + } + } + else + { + Exp = (Zero > A ? Ones : Zeros); + } + + Assert.Multiple(() => + { + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp)); + Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp)); + }); + } + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs b/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs index 498488206e..055e08689c 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs @@ -19,12 +19,13 @@ namespace Ryujinx.Tests.Cpu AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); - Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0); - - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A0)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B0)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A2)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B2)); + Assert.Multiple(() => + { + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A0)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B0)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A2)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B2)); + }); } [Test, Description("TRN1 V0.8B, V1.8B, V2.8B")] @@ -39,14 +40,17 @@ namespace Ryujinx.Tests.Cpu AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A0)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B0)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A2)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B2)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)4), Is.EqualTo(A4)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)5), Is.EqualTo(B4)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)6), Is.EqualTo(A6)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)7), Is.EqualTo(B6)); + Assert.Multiple(() => + { + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A0)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B0)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A2)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B2)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)4), Is.EqualTo(A4)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)5), Is.EqualTo(B4)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)6), Is.EqualTo(A6)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)7), Is.EqualTo(B6)); + }); } [Test, Description("TRN2 V0.4S, V1.4S, V2.4S")] @@ -59,10 +63,13 @@ namespace Ryujinx.Tests.Cpu AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A1)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B1)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A3)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B3)); + Assert.Multiple(() => + { + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A1)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B1)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A3)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B3)); + }); } [Test, Description("TRN2 V0.8B, V1.8B, V2.8B")] @@ -77,14 +84,17 @@ namespace Ryujinx.Tests.Cpu AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A1)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B1)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A3)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B3)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)4), Is.EqualTo(A5)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)5), Is.EqualTo(B5)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)6), Is.EqualTo(A7)); - Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)7), Is.EqualTo(B7)); + Assert.Multiple(() => + { + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)0), Is.EqualTo(A1)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)1), Is.EqualTo(B1)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)2), Is.EqualTo(A3)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)3), Is.EqualTo(B3)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)4), Is.EqualTo(A5)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)5), Is.EqualTo(B5)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)6), Is.EqualTo(A7)); + Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V0), (byte)7), Is.EqualTo(B7)); + }); } [TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]