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Add WZR/WSP tests

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unknown 2018-02-23 23:29:46 +01:00
commit 944e7bc65e
2 changed files with 37 additions and 9 deletions
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7
Ryujinx.Tests/Cpu/CpuTest.cs
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@ -57,13 +57,14 @@ namespace Ryujinx.Tests.Cpu
Position += 4; Position += 4;
} }
protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0,
AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec), AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec),
bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false) bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false)
{ {
Thread.ThreadState.X0 = X0; Thread.ThreadState.X0 = X0;
Thread.ThreadState.X1 = X1; Thread.ThreadState.X1 = X1;
Thread.ThreadState.X2 = X2; Thread.ThreadState.X2 = X2;
Thread.ThreadState.X31 = X31;
Thread.ThreadState.V0 = V0; Thread.ThreadState.V0 = V0;
Thread.ThreadState.V1 = V1; Thread.ThreadState.V1 = V1;
Thread.ThreadState.V2 = V2; Thread.ThreadState.V2 = V2;
@ -91,14 +92,14 @@ namespace Ryujinx.Tests.Cpu
} }
protected AThreadState SingleOpcode(uint Opcode, protected AThreadState SingleOpcode(uint Opcode,
ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0,
AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec), AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec),
bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false) bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false)
{ {
this.Opcode(Opcode); this.Opcode(Opcode);
this.Opcode(0xD4200000); // BRK #0 this.Opcode(0xD4200000); // BRK #0
this.Opcode(0xD65F03C0); // RET this.Opcode(0xD65F03C0); // RET
SetThreadState(X0, X1, X2, V0, V1, V2, Overflow, Carry, Zero, Negative); SetThreadState(X0, X1, X2, X31, V0, V1, V2, Overflow, Carry, Zero, Negative);
ExecuteOpcodes(); ExecuteOpcodes();
return GetThreadState(); return GetThreadState();

39
Ryujinx.Tests/Cpu/CpuTestAlu.cs
View file

@ -7,7 +7,7 @@ namespace Ryujinx.Tests.Cpu
{ {
public void Adc() public void Adc()
{ {
// ADC X0, X1, X2 64bit // ADC X0, X1, X2
AThreadState ThreadState = SingleOpcode(0x9A020020, X1: 2, X2: 3, Carry: true); AThreadState ThreadState = SingleOpcode(0x9A020020, X1: 2, X2: 3, Carry: true);
Assert.AreEqual(6, ThreadState.X0); Assert.AreEqual(6, ThreadState.X0);
@ -18,7 +18,7 @@ namespace Ryujinx.Tests.Cpu
Reset(); Reset();
// ADC W0, W1, W2 32bit // ADC W0, W1, W2
ThreadState = SingleOpcode(0x1A020020, X1: 2, X2: 3, Carry: true); ThreadState = SingleOpcode(0x1A020020, X1: 2, X2: 3, Carry: true);
Assert.AreEqual(6, ThreadState.X0); Assert.AreEqual(6, ThreadState.X0);
@ -32,10 +32,7 @@ namespace Ryujinx.Tests.Cpu
// ADC Overflow // ADC Overflow
ThreadState = SingleOpcode(0x1A020020, X1: 0xFFFFFFFF, X2: 0x2, Carry: false); ThreadState = SingleOpcode(0x1A020020, X1: 0xFFFFFFFF, X2: 0x2, Carry: false);
Assert.AreEqual(0x1, ThreadState.X0); Assert.AreEqual(0x1, ThreadState.X0);
Assert.AreEqual(true, ThreadState.Carry); Assert.IsTrue(ThreadState.Carry);
Reset();
} }
[Test] [Test]
@ -46,6 +43,36 @@ namespace Ryujinx.Tests.Cpu
Assert.AreEqual(3, ThreadState.X0); Assert.AreEqual(3, ThreadState.X0);
} }
[TestCase(2u)]
[TestCase(5u)]
[TestCase(7u)]
[TestCase(0xFFFFFFFFu)]
[TestCase(0xFFFFFFFBu)]
public void Adds(uint A)
{
//ADDS WZR, WSP, #5
AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A);
Assert.IsFalse(ThreadState.Negative);
if(A == 0xFFFFFFFB)
{
Assert.IsTrue(ThreadState.Zero);
}
else
{
Assert.IsFalse(ThreadState.Zero);
}
if(A == 0xFFFFFFFF || A == 0xFFFFFFFB)
{
Assert.IsTrue(ThreadState.Carry);
}
else
{
Assert.IsFalse(ThreadState.Carry);
}
Assert.IsFalse(ThreadState.Overflow);
Assert.AreEqual(A, ThreadState.X31);
}
[TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)] [TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)]
[TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)] [TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)]
[TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)] [TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)]