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More test cleanup

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This commit is contained in:
riperiperi 2020-01-19 21:00:44 +00:00
parent 84991414e1
commit 9be5c4e25b
7 changed files with 105 additions and 68 deletions
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10
Ryujinx.Tests/Cpu/CpuTestAlu32.cs
View file

@ -18,7 +18,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
{
uint opcode = 0xe6ff0f30; // RBIT R0, R0
uint opcode = 0xe6ff0f30u; // RBIT R0, R0
opcode |= ((rm & 15) << 0) | ((rd & 15) << 12);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
@ -33,7 +33,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
[Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
{
uint opcode = 0xe1b00030; // LSRS R0, R0, R0
uint opcode = 0xe1b00030u; // LSRS R0, R0, R0
uint rd = 0;
uint rm = 1;
uint rs = 2;
@ -49,7 +49,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
[Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
{
uint opcode = 0xe1b00010; // LSLS R0, R0, R0
uint opcode = 0xe1b00010u; // LSLS R0, R0, R0
uint rd = 0;
uint rm = 1;
uint rs = 2;
@ -65,7 +65,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
[Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
{
uint opcode = 0xe1b00050; // ASRS R0, R0, R0
uint opcode = 0xe1b00050u; // ASRS R0, R0, R0
uint rd = 0;
uint rm = 1;
uint rs = 2;
@ -81,7 +81,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue,
[Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount)
{
uint opcode = 0xe1b00070; // RORS R0, R0, R0
uint opcode = 0xe1b00070u; // RORS R0, R0, R0
uint rd = 0;
uint rm = 1;
uint rs = 2;

22
Ryujinx.Tests/Cpu/CpuTestAluRs32.cs
View file

@ -8,7 +8,7 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestAluRs32 : CpuTest32
{
#if AluRs32
private const int RndCnt = 50;
private const int RndCnt = 5;
private const int RndCntAmount = 50;
private const int RndCntLsb = 2;
@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0xe0a00000; // ADC R0, R0, R0
uint opcode = 0xe0a00000u; // ADC R0, R0, R0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();
@ -42,7 +42,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0xe0b00000; // ADCS R0, R0, R0
uint opcode = 0xe0b00000u; // ADCS R0, R0, R0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();
@ -63,7 +63,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
{
uint opcode = 0xe0800000; // ADD R0, R0, R0, LSL #0
uint opcode = 0xe0800000u; // ADD R0, R0, R0, LSL #0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
@ -85,7 +85,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
{
uint opcode = 0xe0900000; // ADDS R0, R0, R0, LSL #0
uint opcode = 0xe0900000u; // ADDS R0, R0, R0, LSL #0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
@ -107,7 +107,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
{
uint opcode = 0xe0600000; // RSB R0, R0, R0, LSL #0
uint opcode = 0xe0600000u; // RSB R0, R0, R0, LSL #0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
@ -129,7 +129,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount)
{
uint opcode = 0xe0700000; // RSBS R0, R0, R0, LSL #0
uint opcode = 0xe0700000u; // RSBS R0, R0, R0, LSL #0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
opcode |= ((shift & 3) << 5) | ((amount & 31) << 7);
@ -150,7 +150,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0xe0e00000; // RSC R0, R0, R0
uint opcode = 0xe0e00000u; // RSC R0, R0, R0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();
@ -170,7 +170,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0xe0f00000; // RSCS R0, R0, R0
uint opcode = 0xe0f00000u; // RSCS R0, R0, R0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();
@ -190,7 +190,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0xe0c00000; // SBC R0, R0, R0
uint opcode = 0xe0c00000u; // SBC R0, R0, R0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();
@ -210,7 +210,7 @@ namespace Ryujinx.Tests.Cpu
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values] bool carryIn)
{
uint opcode = 0xe0d00000; // SBCS R0, R0, R0
uint opcode = 0xe0d00000u; // SBCS R0, R0, R0
opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
uint sp = TestContext.CurrentContext.Random.NextUInt();

8
Ryujinx.Tests/Cpu/CpuTestBf32.cs
View file

@ -20,7 +20,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
{
msb = Math.Max(lsb, msb); // don't test unpredictable for now
uint opcode = 0xe7c0001f; // BFC R0, #0, #1
uint opcode = 0xe7c0001fu; // BFC R0, #0, #1
opcode |= ((rd & 0xf) << 12);
opcode |= ((msb & 31) << 16) | ((lsb & 31) << 7);
@ -41,7 +41,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint msb)
{
msb = Math.Max(lsb, msb); // don't test unpredictable for now
uint opcode = 0xe7c00010; // BFI r0, r0, #0, #1
uint opcode = 0xe7c00010u; // BFI R0, R0, #0, #1
opcode |= ((rd & 0xf) << 12);
opcode |= ((rn & 0xf) << 0);
opcode |= ((msb & 31) << 16) | ((lsb & 31) << 7);
@ -66,7 +66,7 @@ namespace Ryujinx.Tests.Cpu
{
widthm1 -= (lsb + widthm1) - 31;
}
uint opcode = 0xe7e00050; // UBFX r0, r0, #0, #1
uint opcode = 0xe7e00050u; // UBFX R0, R0, #0, #1
opcode |= ((rd & 0xf) << 12);
opcode |= ((rn & 0xf) << 0);
opcode |= ((widthm1 & 31) << 16) | ((lsb & 31) << 7);
@ -91,7 +91,7 @@ namespace Ryujinx.Tests.Cpu
{
widthm1 -= (lsb + widthm1) - 31;
}
uint opcode = 0xe7a00050; // SBFX r0, r0, #0, #1
uint opcode = 0xe7a00050u; // SBFX R0, R0, #0, #1
opcode |= ((rd & 0xf) << 12);
opcode |= ((rn & 0xf) << 0);
opcode |= ((widthm1 & 31) << 16) | ((lsb & 31) << 7);

8
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
View file

@ -41,7 +41,7 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCnt)] ulong b,
[Values] bool q)
{
uint opcode = GenerateVectorOpcode(0xf3300110, rd, rn, rm, q);
uint opcode = GenerateVectorOpcode(0xf3300110u, rd, rn, rm, q); // VBIF D0, D0, D0
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
@ -61,7 +61,7 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCnt)] ulong b,
[Values] bool q)
{
uint opcode = GenerateVectorOpcode(0xf3200110, rd, rn, rm, q);
uint opcode = GenerateVectorOpcode(0xf3200110u, rd, rn, rm, q); // VBIT D0, D0, D0
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
@ -81,7 +81,7 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCnt)] ulong b,
[Values] bool q)
{
uint opcode = GenerateVectorOpcode(0xf3100110, rd, rn, rm, q);
uint opcode = GenerateVectorOpcode(0xf3100110u, rd, rn, rm, q); // VBSL D0, D0, D0
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
@ -101,7 +101,7 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCnt)] ulong b,
[Values] bool q)
{
uint opcode = GenerateVectorOpcode(0xf2000110, rd, rn, rm, q);
uint opcode = GenerateVectorOpcode(0xf2000110u, rd, rn, rm, q); // VAND D0, D0, D0
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);

26
Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
View file

@ -49,7 +49,7 @@ namespace Ryujinx.Tests.Cpu
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
uint opcode = 0xf4a00000; // vld1.8 {d0[0]}, [r0], r0
uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15);
@ -67,7 +67,7 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Combinatorial, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (all lanes)")]
[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (all lanes)")]
public void Vldn_All([Values(0u, 13u)] uint rn,
[Values(1u, 13u, 15u)] uint rm,
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
@ -79,7 +79,7 @@ namespace Ryujinx.Tests.Cpu
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
uint opcode = 0xf4a00c00; // vld1.8 {d0[0]}, [r0], r0
uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15);
@ -94,7 +94,7 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Combinatorial, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
public void Vldn_Pair([Values(0u, 1u, 2u, 3u)] uint size,
[Values(0u, 13u)] uint rn,
[Values(1u, 13u, 15u)] uint rm,
@ -105,7 +105,7 @@ namespace Ryujinx.Tests.Cpu
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
uint opcode = 0xf4200000; // vld4.8 {d0, d1, d2, d3}, [r0], r0
uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
@ -131,7 +131,7 @@ namespace Ryujinx.Tests.Cpu
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
uint opcode = 0xf4800000; // vst1.8 {d0[0]}, [r0], r0
uint opcode = 0xf4800000u; // VST1.8 {D0[0]}, [R0], R0
opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15);
@ -149,7 +149,7 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Combinatorial, Description("VSTn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
[Test, Pairwise, Description("VSTn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
public void Vstn_Pair([Values(0u, 1u, 2u, 3u)] uint size,
[Values(0u, 13u)] uint rn,
[Values(1u, 13u, 15u)] uint rm,
@ -161,8 +161,8 @@ namespace Ryujinx.Tests.Cpu
SetWorkingMemory(data);
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
uint opcode = 0xf4000000; // vst4.8 {d0, d1, d2, d3}, [r0], r0
uint opcode = 0xf4000000u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
@ -174,7 +174,7 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Combinatorial, Description("VLDM.<size> <Rn>{!}, <d/sreglist>")]
[Test, Pairwise, Description("VLDM.<size> <Rn>{!}, <d/sreglist>")]
public void Vldm([Values(0u, 13u)] uint rn,
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
[Range(0u, 2u)] uint mode,
@ -184,7 +184,7 @@ namespace Ryujinx.Tests.Cpu
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
uint opcode = 0xec100a00; // vst4.8 {d0, d1, d2, d3}, [r0], r0
uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
uint[] vldmModes = {
//note: 3rd 0 leaves a space for "D"
@ -231,7 +231,7 @@ namespace Ryujinx.Tests.Cpu
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
uint opcode = 0xed900a00; // VLDR.32 S0, [R0, #0]
uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
if (sub)
@ -266,7 +266,7 @@ namespace Ryujinx.Tests.Cpu
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
uint opcode = 0xed800a00; // VSTR.32 S0, [R0, #0]
uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
if (sub)

85
Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs
View file

@ -42,10 +42,13 @@ namespace Ryujinx.Tests.Cpu
};
uint opcode = 0xf2800010; // vmov.i32 d0, #0
uint opcode = 0xf2800010u; // VMOV.I32 D0, #0
uint cmodeOp = variants[variant];
if (q) vd &= 0x1e;
if (q)
{
vd <<= 1;
}
opcode |= ((cmodeOp & 1) << 5) | ((cmodeOp & 0x1e) << 7);
opcode |= ((q ? 1u : 0u) << 6);
@ -60,11 +63,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Combinatorial, Description("VMOV.F<size> <Sd>, #<imm>")]
public void Movi_S([Range(2u, 3u)] uint size, //fp16 is not supported for now
public void Movi_S([Range(2u, 3u)] uint size,
[Values(0u, 1u, 2u, 3u)] uint vd,
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm)
{
uint opcode = 0xeeb00800;
uint opcode = 0xeeb00800u;
opcode |= (size & 3) << 8;
opcode |= (imm & 0xf) | ((imm & 0xf0) << 12);
@ -92,7 +95,7 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCntImm)] ulong valueVn2,
[Values] bool op)
{
uint opcode = 0xee000a10;
uint opcode = 0xee000a10u; // VMOV S0, R0
opcode |= (vn & 1) << 7;
opcode |= (vn & 0x1e) << 15;
opcode |= (rt & 0xf) << 12;
@ -115,7 +118,7 @@ namespace Ryujinx.Tests.Cpu
[Values] bool op,
[Values] bool u)
{
uint opcode = 0xee000b10;
uint opcode = 0xee000b10u; // VMOV.32 D0[0], R0
uint opEncode = 0b01000;
switch (size)
@ -137,8 +140,15 @@ namespace Ryujinx.Tests.Cpu
opcode |= (vn & 0xf) << 16;
opcode |= (rt & 0xf) << 12;
if (op) opcode |= 1 << 20;
if (op && u && size != 2) opcode |= 1 << 23;
if (op)
{
opcode |= 1 << 20;
if (u && size != 2)
{
opcode |= 1 << 23;
}
}
SingleOpcode(opcode, r0: valueRn, r1: valueRn, r2: valueRn, r3: valueRn, v0: new V128(valueVn1, valueVn2), v1: new V128(valueVn2, valueVn1));
@ -155,13 +165,16 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCntImm)] ulong valueVn2,
[Values] bool op)
{
uint opcode = 0xec400b10;
uint opcode = 0xec400b10u; // VMOV D0, R0, R0
opcode |= (vm & 0x10) << 1;
opcode |= (vm & 0xf);
opcode |= (rt & 0xf) << 12;
opcode |= (rt2 & 0xf) << 16;
if (op) opcode |= 1 << 20;
if (op)
{
opcode |= 1 << 20;
}
SingleOpcode(opcode, r0: valueRt1, r1: valueRt2, r2: valueRt1, r3: valueRt2, v0: new V128(valueVn1, valueVn2));
@ -178,13 +191,16 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCntImm)] ulong valueVn2,
[Values] bool op)
{
uint opcode = 0xec400a10;
uint opcode = 0xec400a10u; //VMOV S0, S1, R0, R0
opcode |= (vm & 1) << 5;
opcode |= (vm & 0x1e) >> 1;
opcode |= (rt & 0xf) << 12;
opcode |= (rt2 & 0xf) << 16;
if (op) opcode |= 1 << 20;
if (op)
{
opcode |= 1 << 20;
}
SingleOpcode(opcode, r0: valueRt1, r1: valueRt2, r2: valueRt1, r3: valueRt2, v0: new V128(valueVn1, valueVn2), v1: new V128(valueVn2, valueVn1));
@ -197,8 +213,11 @@ namespace Ryujinx.Tests.Cpu
[Values(0u, 1u, 2u)] uint size,
[Values] bool q)
{
uint opcode = 0xf3b20080;
if (vm == vd) return; //undefined
uint opcode = 0xf3b20080u; // VTRN.8 D0, D0
if (vm == vd)
{
return; //undefined
}
if (q)
{
@ -227,8 +246,11 @@ namespace Ryujinx.Tests.Cpu
[Values(0u, 1u, 2u)] uint size,
[Values] bool q)
{
uint opcode = 0xf3b20180;
if (vm == vd || (size == 2 && !q)) return; //undefined
uint opcode = 0xf3b20180u; // VZIP.8 d0, d0
if (vm == vd || (size == 2 && !q))
{
return; //undefined
}
if (q)
{
@ -257,8 +279,11 @@ namespace Ryujinx.Tests.Cpu
[Values(0u, 1u, 2u)] uint size,
[Values] bool q)
{
uint opcode = 0xf3b20100;
if (vm == vd || (size == 2 && !q)) return; //undefined
uint opcode = 0xf3b20100u; // VUZP.8 d0, d0
if (vm == vd || (size == 2 && !q))
{
return; //undefined
}
if (q)
{
@ -288,8 +313,11 @@ namespace Ryujinx.Tests.Cpu
[Range(0u, 3u)] uint length,
[Values] bool x)
{
uint opcode = 0xf3b00800;
if (vn + length > 31) return; //undefined
uint opcode = 0xf3b00800u; // VTBL.8 D0, {D0}, D0
if (vn + length > 31)
{
return; //undefined
}
if (x)
{
@ -334,14 +362,17 @@ namespace Ryujinx.Tests.Cpu
[Values(0u, 15u)] uint imm4,
[Values] bool q)
{
uint opcode = 0xf2b00000;
uint opcode = 0xf2b00000; // VEXT.32 D0, D0, D0, #0
if (q)
{
opcode |= 1 << 6;
vd <<= 1; vm <<= 1; vn <<= 1;
} else if (imm4 > 7) return; //undefined
}
else if (imm4 > 7)
{
return; //undefined
}
opcode |= (vm & 0x10) << 1;
opcode |= (vm & 0xf);
opcode |= (vd & 0x10) << 18;
@ -360,7 +391,7 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VDUP <Vd>, <Rt>")]
[Test, Pairwise, Description("VDUP.<size> <Vd>, <Rt>")]
public void Vdup_GP([Values(0u, 1u, 2u, 3u)] uint vd,
[Values(0u, 1u, 2u, 3u)] uint rt,
[Values(0u, 1u, 2u)] uint size,
@ -369,7 +400,7 @@ namespace Ryujinx.Tests.Cpu
[Random(RndCntImm)] ulong valueVn2,
[Values] bool q)
{
uint opcode = 0xee800b10;
uint opcode = 0xee800b10; // VDUP.32 d0, r0
if (q)
{
@ -381,8 +412,8 @@ namespace Ryujinx.Tests.Cpu
opcode |= (vd & 0xf) << 16;
opcode |= (rt & 0xf) << 12;
opcode |= (size & 1) << 5; //e
opcode |= (size & 2) << 21; //b
opcode |= (size & 1) << 5; // e
opcode |= (size & 2) << 21; // b
V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());

14
Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs
View file

@ -265,7 +265,10 @@ namespace Ryujinx.Tests.Cpu
}
opcode |= ((size & 3) << 8);
if (e) opcode |= 1 << 7;
if (e)
{
opcode |= 1 << 7;
}
V128 v1 = MakeVectorE0(a);
V128 v2 = MakeVectorE0(b);
@ -293,7 +296,7 @@ namespace Ryujinx.Tests.Cpu
[Values] bool q,
[Values] bool u)
{
uint opcode = 0xf2000400;
uint opcode = 0xf2000400u; // VSHL.S8 D0, D0, D0
if (q)
{
opcode |= 1 << 6;
@ -302,7 +305,10 @@ namespace Ryujinx.Tests.Cpu
rd <<= 1;
}
if (u) opcode |= 1 << 24;
if (u)
{
opcode |= 1 << 24;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
@ -325,7 +331,7 @@ namespace Ryujinx.Tests.Cpu
[Range(0u, 7u)] uint rm)
{
// not currently a slow path test - just a sanity check for pairwise
uint opcode = 0xf3000d00u;
uint opcode = 0xf3000d00u; // VPADD.F32 D0, D0, D0
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);