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Update CpuTestSimdRegElem.cs

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LDj3SNuD 2018-10-13 01:12:34 +02:00 • committed by GitHub
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1 changed files with 56 additions and 89 deletions
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Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs
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@ -13,7 +13,7 @@ namespace Ryujinx.Tests.Cpu
{ {
#if SimdRegElem #if SimdRegElem
#region "ValueSource" #region "ValueSource (Types)"
private static ulong[] _2S_() private static ulong[] _2S_()
{ {
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
@ -27,114 +27,81 @@ namespace Ryujinx.Tests.Cpu
} }
#endregion #endregion
#region "ValueSource (Opcodes)"
private static uint[] _Mla_Mls_Mul_Ve_4H_8H_()
{
return new uint[]
{
0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
0x0F408000u // MUL V0.4H, V0.4H, V0.H[0]
};
}
private static uint[] _Mla_Mls_Mul_Ve_2S_4S_()
{
return new uint[]
{
0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
0x0F808000u // MUL V0.2S, V0.2S, V0.S[0]
};
}
#endregion
private const int RndCnt = 2; private const int RndCnt = 2;
[Test, Pairwise, Description("MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")] [Test, Pairwise]
public void Mla_Ve_4H_8H([Values(0u)] uint Rd, public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint Opcodes,
[Values(1u, 0u)] uint Rn, [Values(0u)] uint Rd,
[Values(2u, 0u)] uint Rm, [Values(1u, 0u)] uint Rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong Z, [Values(2u, 0u)] uint Rm,
[ValueSource("_4H_")] [Random(RndCnt)] ulong A, [ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong B, [ValueSource("_4H_")] [Random(RndCnt)] ulong A,
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index, [ValueSource("_4H_")] [Random(RndCnt)] ulong B,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H> [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{ {
uint H = (Index & 4) >> 2; uint H = (Index >> 2) & 1;
uint L = (Index & 2) >> 1; uint L = (Index >> 1) & 1;
uint M = (Index & 1) >> 0; uint M = Index & 1;
uint Opcode = 0x2F400000; // MLA V0.4H, V0.4H, V0.H[0] Opcodes |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcodes |= (L << 21) | (M << 20) | (H << 11);
Opcode |= (L << 21) | (M << 20) | (H << 11); Opcodes |= ((Q & 1) << 30);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z); Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q); Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H); Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn(); CompareAgainstUnicorn();
} }
[Test, Pairwise, Description("MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")] [Test, Pairwise]
public void Mla_Ve_2S_4S([Values(0u)] uint Rd, public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint Opcodes,
[Values(1u, 0u)] uint Rn, [Values(0u)] uint Rd,
[Values(2u, 0u)] uint Rm, [Values(1u, 0u)] uint Rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong Z, [Values(2u, 0u)] uint Rm,
[ValueSource("_2S_")] [Random(RndCnt)] ulong A, [ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong B, [ValueSource("_2S_")] [Random(RndCnt)] ulong A,
[Values(0u, 1u, 2u, 3u)] uint Index, [ValueSource("_2S_")] [Random(RndCnt)] ulong B,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S> [Values(0u, 1u, 2u, 3u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{ {
uint H = (Index & 2) >> 1; uint H = (Index >> 1) & 1;
uint L = (Index & 1) >> 0; uint L = Index & 1;
uint Opcode = 0x2F800000; // MLA V0.2S, V0.2S, V0.S[0] Opcodes |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcodes |= (L << 21) | (H << 11);
Opcode |= (L << 21) | (H << 11); Opcodes |= ((Q & 1) << 30);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z); Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q); Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H); Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
public void Mls_Ve_4H_8H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong A,
[ValueSource("_4H_")] [Random(RndCnt)] ulong B,
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{
uint H = (Index & 4) >> 2;
uint L = (Index & 2) >> 1;
uint M = (Index & 1) >> 0;
uint Opcode = 0x2F404000; // MLS V0.4H, V0.4H, V0.H[0]
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (L << 21) | (M << 20) | (H << 11);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
public void Mls_Ve_2S_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_2S_")] [Random(RndCnt)] ulong B,
[Values(0u, 1u, 2u, 3u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{
uint H = (Index & 2) >> 1;
uint L = (Index & 1) >> 0;
uint Opcode = 0x2F804000; // MLS V0.2S, V0.2S, V0.S[0]
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (L << 21) | (H << 11);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn(); CompareAgainstUnicorn();
} }