Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions

This commit is contained in:
gdkchan 2020-02-26 22:00:34 -03:00
commit 9eb06f7879
7 changed files with 410 additions and 190 deletions

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@ -692,13 +692,15 @@ namespace ARMeilleure.Decoders
SetA32("<<<<0000110xxxxxxxxxxxxx0xx1xxxx", InstName.Sbc, InstEmit32.Sbc, typeof(OpCode32AluRsReg));
SetA32("<<<<0111101xxxxxxxxxxxxxx101xxxx", InstName.Sbfx, InstEmit32.Sbfx, typeof(OpCode32AluBf));
SetA32("<<<<01110001xxxx1111xxxx0001xxxx", InstName.Sdiv, InstEmit32.Sdiv, typeof(OpCode32AluMla));
SetA32("<<<<00010000xxxxxxxxxxxx1xx0xxxx", InstName.Smlab, InstEmit32.Smlab, typeof(OpCode32AluMla));
SetA32("<<<<00010000xxxxxxxxxxxx1xx0xxxx", InstName.Smla__, InstEmit32.Smla__, typeof(OpCode32AluMla));
SetA32("<<<<0000111xxxxxxxxxxxxx1001xxxx", InstName.Smlal, InstEmit32.Smlal, typeof(OpCode32AluUmull));
SetA32("<<<<00010100xxxxxxxxxxxx1xx0xxxx", InstName.Smlalh, InstEmit32.Smlalh, typeof(OpCode32AluUmull));
SetA32("<<<<00010100xxxxxxxxxxxx1xx0xxxx", InstName.Smlal__, InstEmit32.Smlal__, typeof(OpCode32AluUmull));
SetA32("<<<<00010010xxxxxxxxxxxx1x00xxxx", InstName.Smlaw_, InstEmit32.Smlaw_, typeof(OpCode32AluMla));
SetA32("<<<<01110101xxxxxxxxxxxx00x1xxxx", InstName.Smmla, InstEmit32.Smmla, typeof(OpCode32AluMla));
SetA32("<<<<01110101xxxxxxxxxxxx11x1xxxx", InstName.Smmls, InstEmit32.Smmls, typeof(OpCode32AluMla));
SetA32("<<<<00010110xxxxxxxxxxxx1xx0xxxx", InstName.Smulh, InstEmit32.Smulh, typeof(OpCode32AluMla));
SetA32("<<<<0000110xxxxxxxxxxxxx1001xxxx", InstName.Smull, InstEmit32.Smull, typeof(OpCode32AluUmull));
SetA32("<<<<00010010xxxx0000xxxx1x10xxxx", InstName.Smulw_, InstEmit32.Smulw_, typeof(OpCode32AluMla));
SetA32("<<<<00011000xxxx111111001001xxxx", InstName.Stl, InstEmit32.Stl, typeof(OpCode32MemStEx));
SetA32("<<<<00011100xxxx111111001001xxxx", InstName.Stlb, InstEmit32.Stlb, typeof(OpCode32MemStEx));
SetA32("<<<<00011000xxxxxxxx11101001xxxx", InstName.Stlex, InstEmit32.Stlex, typeof(OpCode32MemStEx));

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@ -1,5 +1,6 @@
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
@ -53,27 +54,6 @@ namespace ARMeilleure.Instructions
EmitAluStore(context, res);
}
public static void Smull(ArmEmitterContext context)
{
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
Operand res = context.Multiply(n, m);
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
Operand lo = context.ConvertI64ToI32(res);
if (op.SetFlags)
{
EmitNZFlagsCheck(context, res);
}
EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
}
public static void Smmla(ArmEmitterContext context)
{
EmitSmmul(context, MullFlags.SignedAdd);
@ -117,37 +97,40 @@ namespace ARMeilleure.Instructions
EmitGenericAluStoreA32(context, op.Rd, false, hi);
}
public static void Smlab(ArmEmitterContext context)
public static void Smla__(ArmEmitterContext context)
{
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
Operand n = GetIntA32(context, op.Rn);
Operand m = GetIntA32(context, op.Rm);
Operand a = GetIntA32(context, op.Ra);
if (op.NHigh)
{
n = context.SignExtend16(OperandType.I32, context.ShiftRightUI(n, Const(16)));
n = context.SignExtend16(OperandType.I64, context.ShiftRightUI(n, Const(16)));
}
else
{
n = context.SignExtend16(OperandType.I32, n);
n = context.SignExtend16(OperandType.I64, n);
}
if (op.MHigh)
{
m = context.SignExtend16(OperandType.I32, context.ShiftRightUI(m, Const(16)));
m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
}
else
{
m = context.SignExtend16(OperandType.I32, m);
m = context.SignExtend16(OperandType.I64, m);
}
Operand res = context.Multiply(n, m);
Operand a = GetIntA32(context, op.Ra);
res = context.Add(res, a);
Operand toAdd = context.SignExtend32(OperandType.I64, a);
res = context.Add(res, toAdd);
Operand q = context.ICompareNotEqual(res, context.SignExtend32(OperandType.I64, res));
res = context.ConvertI64ToI32(res);
// TODO: set Q flag when last addition overflows (saturation)?
UpdateQFlag(context, q);
EmitGenericAluStoreA32(context, op.Rd, false, res);
}
@ -157,7 +140,7 @@ namespace ARMeilleure.Instructions
EmitMlal(context, true);
}
public static void Smlalh(ArmEmitterContext context)
public static void Smlal__(ArmEmitterContext context)
{
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
@ -195,6 +178,36 @@ namespace ARMeilleure.Instructions
EmitGenericAluStoreA32(context, op.RdLo, false, lo);
}
public static void Smlaw_(ArmEmitterContext context)
{
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
Operand n = GetIntA32(context, op.Rn);
Operand m = GetIntA32(context, op.Rm);
Operand a = GetIntA32(context, op.Ra);
if (op.MHigh)
{
m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
}
else
{
m = context.SignExtend16(OperandType.I64, m);
}
Operand res = context.Multiply(context.SignExtend32(OperandType.I64, n), m);
Operand toAdd = context.ShiftLeft(context.SignExtend32(OperandType.I64, a), Const(16));
res = context.Add(res, toAdd);
res = context.ShiftRightSI(res, Const(16));
Operand q = context.ICompareNotEqual(res, context.SignExtend32(OperandType.I64, res));
res = context.ConvertI64ToI32(res);
UpdateQFlag(context, q);
EmitGenericAluStoreA32(context, op.Rd, false, res);
}
public static void Smulh(ArmEmitterContext context)
{
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
@ -225,6 +238,51 @@ namespace ARMeilleure.Instructions
EmitGenericAluStoreA32(context, op.Rd, false, res);
}
public static void Smull(ArmEmitterContext context)
{
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
Operand res = context.Multiply(n, m);
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
Operand lo = context.ConvertI64ToI32(res);
if (op.SetFlags)
{
EmitNZFlagsCheck(context, res);
}
EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
}
public static void Smulw_(ArmEmitterContext context)
{
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
Operand n = GetIntA32(context, op.Rn);
Operand m = GetIntA32(context, op.Rm);
if (op.MHigh)
{
m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
}
else
{
m = context.SignExtend16(OperandType.I64, m);
}
Operand res = context.Multiply(context.SignExtend32(OperandType.I64, n), m);
res = context.ShiftRightUI(res, Const(16));
res = context.ConvertI64ToI32(res);
EmitGenericAluStoreA32(context, op.Rd, false, res);
}
public static void Umlal(ArmEmitterContext context)
{
EmitMlal(context, false);
@ -286,5 +344,16 @@ namespace ARMeilleure.Instructions
EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
}
private static void UpdateQFlag(ArmEmitterContext context, Operand q)
{
Operand lblSkipSetQ = Label();
context.BranchIfFalse(lblSkipSetQ, q);
SetFlag(context, PState.QFlag, Const(1));
context.MarkLabel(lblSkipSetQ);
}
}
}

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@ -83,6 +83,7 @@ namespace ARMeilleure.Instructions
Smsubl,
Smulh,
Smull,
Smulw_,
Stlr,
Stlxp,
Stlxr,
@ -487,9 +488,10 @@ namespace ARMeilleure.Instructions
Rsb,
Rsc,
Sbfx,
Smlab,
Smla__,
Smlal,
Smlalh,
Smlal__,
Smlaw_,
Smmla,
Smmls,
Smmul,

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@ -7,7 +7,7 @@ namespace ARMeilleure.State
{
TFlag = 5,
EFlag = 9,
QFlag = 27,
VFlag = 28,
CFlag = 29,
ZFlag = 30,

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@ -45,10 +45,10 @@ namespace Ryujinx.Tests.Unicorn
set => SetRegister(Arm32Register.PC, value);
}
public uint APSR
public uint CPSR
{
get => (uint)GetRegister(Arm32Register.APSR);
set => SetRegister(Arm32Register.APSR, (uint)value);
get => (uint)GetRegister(Arm32Register.CPSR);
set => SetRegister(Arm32Register.CPSR, (uint)value);
}
public int Fpscr
@ -57,28 +57,34 @@ namespace Ryujinx.Tests.Unicorn
set => SetRegister(Arm32Register.FPSCR, (uint)value);
}
public bool QFlag
{
get => (CPSR & 0x8000000u) != 0;
set => CPSR = (CPSR & ~0x8000000u) | (value ? 0x8000000u : 0u);
}
public bool OverflowFlag
{
get => (APSR & 0x10000000u) != 0;
set => APSR = (APSR & ~0x10000000u) | (value ? 0x10000000u : 0u);
get => (CPSR & 0x10000000u) != 0;
set => CPSR = (CPSR & ~0x10000000u) | (value ? 0x10000000u : 0u);
}
public bool CarryFlag
{
get => (APSR & 0x20000000u) != 0;
set => APSR = (APSR & ~0x20000000u) | (value ? 0x20000000u : 0u);
get => (CPSR & 0x20000000u) != 0;
set => CPSR = (CPSR & ~0x20000000u) | (value ? 0x20000000u : 0u);
}
public bool ZeroFlag
{
get => (APSR & 0x40000000u) != 0;
set => APSR = (APSR & ~0x40000000u) | (value ? 0x40000000u : 0u);
get => (CPSR & 0x40000000u) != 0;
set => CPSR = (CPSR & ~0x40000000u) | (value ? 0x40000000u : 0u);
}
public bool NegativeFlag
{
get => (APSR & 0x80000000u) != 0;
set => APSR = (APSR & ~0x80000000u) | (value ? 0x80000000u : 0u);
get => (CPSR & 0x80000000u) != 0;
set => CPSR = (CPSR & ~0x80000000u) | (value ? 0x80000000u : 0u);
}
public UnicornAArch32()

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@ -348,6 +348,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That((int)_context.Fpcr | ((int)_context.Fpsr & (int)fpsrMask), Is.EqualTo(_unicornEmu.Fpscr));
Assert.That(_context.GetPstateFlag(PState.QFlag), Is.EqualTo(_unicornEmu.QFlag));
Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag));
Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag));
Assert.That(_context.GetPstateFlag(PState.ZFlag), Is.EqualTo(_unicornEmu.ZeroFlag));

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@ -0,0 +1,140 @@
#define Mul32
using NUnit.Framework;
using System;
namespace Ryujinx.Tests.Cpu
{
[Category("Mul32")]
public sealed class CpuTestMul32 : CpuTest32
{
#if Mul32
#region "ValueSource (Opcodes)"
private static uint[] _Smlabb_Smlabt_Smlatb_Smlatt_()
{
return new uint[]
{
0xe1000080u, // SMLABB R0, R0, R0, R0
0xe10000C0u, // SMLABT R0, R0, R0, R0
0xe10000A0u, // SMLATB R0, R0, R0, R0
0xe10000E0u, // SMLATT R0, R0, R0, R0
};
}
private static uint[] _Smlawb_Smlawt_()
{
return new uint[]
{
0xe1200080u, // SMLAWB R0, R0, R0, R0
0xe12000C0u, // SMLAWT R0, R0, R0, R0
};
}
private static uint[] _Smulbb_Smulbt_Smultb_Smultt_()
{
return new uint[]
{
0xe1600080u, // SMULBB R0, R0, R0
0xe16000C0u, // SMULBT R0, R0, R0
0xe16000A0u, // SMULTB R0, R0, R0
0xe16000E0u, // SMULTT R0, R0, R0
};
}
private static uint[] _Smulwb_Smulwt_()
{
return new uint[]
{
0xe12000a0u, // SMULWB R0, R0, R0
0xe12000e0u, // SMULWT R0, R0, R0
};
}
#endregion
private const int RndCnt = 2;
[Test, Pairwise, Description("SMLABB/BT/TB/TT <Rd>, <Rn>, <Rm>, <Ra>")]
public void Smla___32bit([ValueSource("_Smlabb_Smlabt_Smlatb_Smlatt_")] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint ra,
[Values(3u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, r0: wn, r1: wm, r2: wa, sp: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SMLAWB/T <Rd>, <Rn>, <Rm>, <Ra>")]
public void Smlaw__32bit([ValueSource("_Smlawb_Smlawt_")] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint ra,
[Values(3u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, r0: wn, r1: wm, r2: wa, sp: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SMULBB/BT/TB/TT <Rd>, <Rn>, <Rm>")]
public void Smul___32bit([ValueSource("_Smulbb_Smulbt_Smultb_Smultt_")] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, r0: wn, r1: wm, sp: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SMULWB/T <Rd>, <Rn>, <Rm>")]
public void Smulw__32bit([ValueSource("_Smulwb_Smulwt_")] uint opcode,
[Values(0u, 0xdu)] uint rn,
[Values(1u, 0xdu)] uint rm,
[Values(2u, 0xdu)] uint rd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
{
opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
SingleOpcode(opcode, r0: wn, r1: wm, sp: w31);
CompareAgainstUnicorn();
}
#endif
}
}