mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Update AInstEmitSimdArithmetic.cs

Browse source
This commit is contained in:
LDj3SNuD 2018-08-11 00:44:07 +02:00 • committed by GitHub
commit a0216568b3
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 55 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

55
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -158,6 +158,41 @@ namespace ChocolArm64.Instruction
Context.MarkLabel(LblTrue); Context.MarkLabel(LblTrue);
} }
private static void EmitAddLongPairwise(AILEmitterCtx Context, bool Signed, bool Accumulate)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Words = Op.GetBitsCount() >> 4;
int Pairs = Words >> Op.Size;
for (int Index = 0; Index < Pairs; Index++)
{
int Idx = Index << 1;
EmitVectorExtract(Context, Op.Rn, Idx, Op.Size, Signed);
EmitVectorExtract(Context, Op.Rn, Idx + 1, Op.Size, Signed);
Context.Emit(OpCodes.Add);
if (Accumulate)
{
EmitVectorExtract(Context, Op.Rd, Index, Op.Size + 1, Signed);
Context.Emit(OpCodes.Add);
}
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round) private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round)
{ {
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -992,6 +1027,16 @@ namespace ChocolArm64.Instruction
}); });
} }
public static void Sadalp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: true, Accumulate: true);
}
public static void Saddlp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: true, Accumulate: false);
}
public static void Saddw_V(AILEmitterCtx Context) public static void Saddw_V(AILEmitterCtx Context)
{ {
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add)); EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
@ -1213,11 +1258,21 @@ namespace ChocolArm64.Instruction
}); });
} }
public static void Uadalp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: false, Accumulate: true);
}
public static void Uaddl_V(AILEmitterCtx Context) public static void Uaddl_V(AILEmitterCtx Context)
{ {
EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add)); EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
} }
public static void Uaddlp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: false, Accumulate: false);
}
public static void Uaddlv_V(AILEmitterCtx Context) public static void Uaddlv_V(AILEmitterCtx Context)
{ {
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;