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Update Instructions.cs

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LDj3SNuD 2018-08-28 19:34:25 +02:00 • committed by GitHub
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Ryujinx.Tests/Cpu/Tester/Instructions.cs
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@ -5481,6 +5481,116 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result); V(d, result);
} }
// smlal_advsimd_vec.html
public static void Smlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool o1 = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
Bits operand3 = V(2 * datasize, d);
BigInteger element1;
BigInteger element2;
Bits product;
Bits accum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
if (sub_op)
{
accum = Elem(operand3, e, 2 * esize) - product;
}
else
{
accum = Elem(operand3, e, 2 * esize) + product;
}
Elem(result, e, 2 * esize, accum);
}
V(d, result);
}
// smlsl_advsimd_vec.html
public static void Smlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
const bool o1 = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
Bits operand3 = V(2 * datasize, d);
BigInteger element1;
BigInteger element2;
Bits product;
Bits accum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
if (sub_op)
{
accum = Elem(operand3, e, 2 * esize) - product;
}
else
{
accum = Elem(operand3, e, 2 * esize) + product;
}
Elem(result, e, 2 * esize, accum);
}
V(d, result);
}
// sqadd_advsimd.html#SQADD_asisdsame_only // sqadd_advsimd.html#SQADD_asisdsame_only
public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd) public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{ {
@ -6493,6 +6603,116 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result); V(d, result);
} }
// umlal_advsimd_vec.html
public static void Umlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool o1 = false;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
Bits operand3 = V(2 * datasize, d);
BigInteger element1;
BigInteger element2;
Bits product;
Bits accum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
if (sub_op)
{
accum = Elem(operand3, e, 2 * esize) - product;
}
else
{
accum = Elem(operand3, e, 2 * esize) + product;
}
Elem(result, e, 2 * esize, accum);
}
V(d, result);
}
// umlsl_advsimd_vec.html
public static void Umlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
const bool o1 = true;
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = 64;
int part = (int)UInt(Q);
int elements = datasize / esize;
bool sub_op = (o1 == true);
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(2 * datasize);
Bits operand1 = Vpart(datasize, n, part);
Bits operand2 = Vpart(datasize, m, part);
Bits operand3 = V(2 * datasize, d);
BigInteger element1;
BigInteger element2;
Bits product;
Bits accum;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
product = (element1 * element2).SubBigInteger(2 * esize - 1, 0);
if (sub_op)
{
accum = Elem(operand3, e, 2 * esize) - product;
}
else
{
accum = Elem(operand3, e, 2 * esize) + product;
}
Elem(result, e, 2 * esize, accum);
}
V(d, result);
}
// uqadd_advsimd.html#UQADD_asisdsame_only // uqadd_advsimd.html#UQADD_asisdsame_only
public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd) public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{ {