From e502650787e93e651830cfd2967e94edfba2e693 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 14 Jul 2018 14:25:11 +0200 Subject: [PATCH 1/4] Implement FCVTNS_V --- ChocolArm64/AOpCodeTable.cs | 1 + ChocolArm64/Instruction/AInstEmitSimdCvt.cs | 25 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index fb4763ef8c..cff15fee65 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -250,6 +250,7 @@ namespace ChocolArm64 SetA64("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp, typeof(AOpCodeSimdCvt)); SetA64("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp, typeof(AOpCodeSimdCvt)); SetA64("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V, typeof(AOpCodeSimd)); + SetA64("0x0011100x100001101010xxxxxxxxxx", AInstEmit.Fcvtns_V, typeof(AOpCodeSimd)); SetA64("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp, typeof(AOpCodeSimdCvt)); SetA64("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp, typeof(AOpCodeSimdCvt)); SetA64("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp, typeof(AOpCodeSimdCvt)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs index da584743c3..8e749a3fc1 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs @@ -105,6 +105,31 @@ namespace ChocolArm64.Instruction EmitVectorZeroUpper(Context, Op.Rd); } } + + public static void Fcvtns_V(AILEmitterCtx Context) + { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + int SizeF = Op.Size & 1; + + int Elems = 4 >> SizeF; + + for (int Index = 0; Index < Elems; Index++) + { + EmitVectorExtractF(Context, Op.Rd, Index, SizeF); + + EmitRoundMathCall(Context, MidpointRounding.ToEven); + + EmitVectorInsertF(Context, Op.Rd, Index, 0); + + } + + if (Op.RegisterSize == ARegisterSize.SIMD64) + { + EmitVectorZeroUpper(Context, Op.Rd); + } + + } public static void Fcvtps_Gp(AILEmitterCtx Context) { From 17673b675d07195467b924ab1fb95937a73f94b2 Mon Sep 17 00:00:00 2001 From: greggameplayer <33609333+greggameplayer@users.noreply.github.com> Date: Fri, 20 Jul 2018 14:56:05 +0200 Subject: [PATCH 2/4] add conversion to signed int --- ChocolArm64/Instruction/AInstEmitSimdCvt.cs | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs index 8e749a3fc1..9cf5edacd0 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs @@ -119,6 +119,15 @@ namespace ChocolArm64.Instruction EmitVectorExtractF(Context, Op.Rd, Index, SizeF); EmitRoundMathCall(Context, MidpointRounding.ToEven); + + if (Op.RegisterSize == ARegisterSize.SIMD64) + { + Context.Emit(OpCodes.Conv_I4); + } + else if (Op.RegisterSize == ARegisterSize.SIMD128) + { + Context.Emit(OpCodes.Conv_I8); + } EmitVectorInsertF(Context, Op.Rd, Index, 0); @@ -127,8 +136,7 @@ namespace ChocolArm64.Instruction if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); - } - + } } public static void Fcvtps_Gp(AILEmitterCtx Context) @@ -594,4 +602,4 @@ namespace ChocolArm64.Instruction } } } -} \ No newline at end of file +} From d5c1d847d71968030348fa3d5520a74b21f4cd99 Mon Sep 17 00:00:00 2001 From: greggameplayer <33609333+greggameplayer@users.noreply.github.com> Date: Fri, 20 Jul 2018 14:56:48 +0200 Subject: [PATCH 3/4] correct alignment --- ChocolArm64/Instruction/AInstEmitSimdCvt.cs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs index 9cf5edacd0..6a3754e6d1 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs @@ -120,7 +120,7 @@ namespace ChocolArm64.Instruction EmitRoundMathCall(Context, MidpointRounding.ToEven); - if (Op.RegisterSize == ARegisterSize.SIMD64) + if (Op.RegisterSize == ARegisterSize.SIMD64) { Context.Emit(OpCodes.Conv_I4); } From eeb86d4135ce136925abcfd5bb68bbd0b7865266 Mon Sep 17 00:00:00 2001 From: greggameplayer <33609333+greggameplayer@users.noreply.github.com> Date: Fri, 20 Jul 2018 14:57:34 +0200 Subject: [PATCH 4/4] final alignment correction --- ChocolArm64/Instruction/AInstEmitSimdCvt.cs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs index 6a3754e6d1..48c3ab0a4e 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdCvt.cs @@ -120,7 +120,7 @@ namespace ChocolArm64.Instruction EmitRoundMathCall(Context, MidpointRounding.ToEven); - if (Op.RegisterSize == ARegisterSize.SIMD64) + if (Op.RegisterSize == ARegisterSize.SIMD64) { Context.Emit(OpCodes.Conv_I4); }