From a94df7a4a257d6a293ffb7fb6a19dd7f5c92bd3a Mon Sep 17 00:00:00 2001 From: gdkchan Date: Tue, 22 Jan 2019 21:35:35 -0200 Subject: [PATCH] Align code again --- ChocolArm64/Decoders/OpCodeCcmp64.cs | 4 ++-- ChocolArm64/Decoders/OpCodeCsel64.cs | 2 +- ChocolArm64/Decoders/OpCodeSimdFcond64.cs | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/ChocolArm64/Decoders/OpCodeCcmp64.cs b/ChocolArm64/Decoders/OpCodeCcmp64.cs index 7cede5f774..d65a24a47e 100644 --- a/ChocolArm64/Decoders/OpCodeCcmp64.cs +++ b/ChocolArm64/Decoders/OpCodeCcmp64.cs @@ -21,9 +21,9 @@ namespace ChocolArm64.Decoders return; } - Nzcv = (opCode >> 0) & 0xf; + Nzcv = (opCode >> 0) & 0xf; Cond = (Condition)((opCode >> 12) & 0xf); - RmImm = (opCode >> 16) & 0x1f; + RmImm = (opCode >> 16) & 0x1f; Rd = RegisterAlias.Zr; } diff --git a/ChocolArm64/Decoders/OpCodeCsel64.cs b/ChocolArm64/Decoders/OpCodeCsel64.cs index f2ceb33800..108a279836 100644 --- a/ChocolArm64/Decoders/OpCodeCsel64.cs +++ b/ChocolArm64/Decoders/OpCodeCsel64.cs @@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode) { - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; Cond = (Condition)((opCode >> 12) & 0xf); } } diff --git a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs index ea1e03d5a2..47de231c2e 100644 --- a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs +++ b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs @@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode) { - Nzcv = (opCode >> 0) & 0xf; + Nzcv = (opCode >> 0) & 0xf; Cond = (Condition)((opCode >> 12) & 0xf); } }