From b3663af7b6c5b7f4ddab6379901b9a4a09738873 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Thu, 23 Aug 2018 20:38:37 +0200
Subject: [PATCH] Update CpuTestSimd.cs

---
 Ryujinx.Tests/Cpu/CpuTestSimd.cs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 68e2d721d5..d1832ce89b 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -1245,11 +1245,11 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests.
+        [Test, Pairwise, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")]
         public void Sha256su0_V([Values(0u)]     uint Rd,
                                 [Values(1u, 0u)] uint Rn,
-                                [Random(5)] ulong Z0, [Random(5)] ulong Z1,
-                                [Random(5)] ulong A0, [Random(5)] ulong A1)
+                                [Random(RndCnt * 2)] ulong Z0, [Random(RndCnt * 2)] ulong Z1,
+                                [Random(RndCnt * 2)] ulong A0, [Random(RndCnt * 2)] ulong A1)
         {
             uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S
             Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);