From b41a32f2ea31c5f7be1511e20fa4f620d3ca3ba9 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Mon, 3 Sep 2018 03:20:36 +0200 Subject: [PATCH] Add files via upload --- Ryujinx.Tests/Cpu/CpuTest.cs | 84 +- Ryujinx.Tests/Cpu/CpuTestAlu.cs | 223 +-- Ryujinx.Tests/Cpu/CpuTestAluImm.cs | 556 +----- Ryujinx.Tests/Cpu/CpuTestAluRs.cs | 1337 +++------------ Ryujinx.Tests/Cpu/CpuTestAluRx.cs | 825 ++------- Ryujinx.Tests/Cpu/CpuTestBfm.cs | 159 +- Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs | 99 +- Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs | 102 +- Ryujinx.Tests/Cpu/CpuTestCsel.cs | 189 +-- Ryujinx.Tests/Cpu/CpuTestMisc.cs | 62 +- Ryujinx.Tests/Cpu/CpuTestMov.cs | 127 +- Ryujinx.Tests/Cpu/CpuTestMul.cs | 257 +-- Ryujinx.Tests/Cpu/CpuTestSimd.cs | 992 +---------- Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 351 ++-- Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs | 52 +- Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | 8 + Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs | 2 + Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 1772 ++------------------ 18 files changed, 1268 insertions(+), 5929 deletions(-) diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs index 6e013aa055..c37d024f72 100644 --- a/Ryujinx.Tests/Cpu/CpuTest.cs +++ b/Ryujinx.Tests/Cpu/CpuTest.cs @@ -33,9 +33,10 @@ namespace Ryujinx.Tests.Cpu static CpuTest() { UnicornAvailable = UnicornAArch64.IsAvailable(); + if (!UnicornAvailable) { - Console.WriteLine("WARNING: Could not find unicorn"); + Console.WriteLine("WARNING: Could not find Unicorn."); } } @@ -43,7 +44,7 @@ namespace Ryujinx.Tests.Cpu public void Setup() { Position = 0x1000; - Size = 0x1000; + Size = 0x1000; EntryPoint = Position; @@ -79,10 +80,12 @@ namespace Ryujinx.Tests.Cpu protected void Opcode(uint Opcode) { Thread.Memory.WriteUInt32(Position, Opcode); + if (UnicornAvailable) { UnicornEmu.MemoryWrite32((ulong)Position, Opcode); } + Position += 4; } @@ -97,14 +100,18 @@ namespace Ryujinx.Tests.Cpu Thread.ThreadState.X1 = X1; Thread.ThreadState.X2 = X2; Thread.ThreadState.X3 = X3; + Thread.ThreadState.X31 = X31; + Thread.ThreadState.V0 = V0; Thread.ThreadState.V1 = V1; Thread.ThreadState.V2 = V2; + Thread.ThreadState.Overflow = Overflow; - Thread.ThreadState.Carry = Carry; - Thread.ThreadState.Zero = Zero; + Thread.ThreadState.Carry = Carry; + Thread.ThreadState.Zero = Zero; Thread.ThreadState.Negative = Negative; + Thread.ThreadState.Fpcr = Fpcr; Thread.ThreadState.Fpsr = Fpsr; @@ -114,14 +121,18 @@ namespace Ryujinx.Tests.Cpu UnicornEmu.X[1] = X1; UnicornEmu.X[2] = X2; UnicornEmu.X[3] = X3; + UnicornEmu.SP = X31; + UnicornEmu.Q[0] = V0; UnicornEmu.Q[1] = V1; UnicornEmu.Q[2] = V2; + UnicornEmu.OverflowFlag = Overflow; - UnicornEmu.CarryFlag = Carry; - UnicornEmu.ZeroFlag = Zero; + UnicornEmu.CarryFlag = Carry; + UnicornEmu.ZeroFlag = Zero; UnicornEmu.NegativeFlag = Negative; + UnicornEmu.Fpcr = Fpcr; UnicornEmu.Fpsr = Fpsr; } @@ -144,10 +155,7 @@ namespace Ryujinx.Tests.Cpu } } - protected AThreadState GetThreadState() - { - return Thread.ThreadState; - } + protected AThreadState GetThreadState() => Thread.ThreadState; protected AThreadState SingleOpcode(uint Opcode, ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0, @@ -173,16 +181,20 @@ namespace Ryujinx.Tests.Cpu return; } - Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0])); - Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1])); - Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2])); - Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3])); - Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4])); - Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5])); - Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6])); - Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7])); - Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8])); - Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9])); + const int QCFlagBit = 27; // Cumulative saturation bit. + + int FpsrMask = 1 << QCFlagBit; + + Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0])); + Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1])); + Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2])); + Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3])); + Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4])); + Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5])); + Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6])); + Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7])); + Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8])); + Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9])); Assert.That(Thread.ThreadState.X10, Is.EqualTo(UnicornEmu.X[10])); Assert.That(Thread.ThreadState.X11, Is.EqualTo(UnicornEmu.X[11])); Assert.That(Thread.ThreadState.X12, Is.EqualTo(UnicornEmu.X[12])); @@ -204,17 +216,19 @@ namespace Ryujinx.Tests.Cpu Assert.That(Thread.ThreadState.X28, Is.EqualTo(UnicornEmu.X[28])); Assert.That(Thread.ThreadState.X29, Is.EqualTo(UnicornEmu.X[29])); Assert.That(Thread.ThreadState.X30, Is.EqualTo(UnicornEmu.X[30])); + Assert.That(Thread.ThreadState.X31, Is.EqualTo(UnicornEmu.SP)); - Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0])); - Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1])); - Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2])); - Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3])); - Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4])); - Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5])); - Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6])); - Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7])); - Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8])); - Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9])); + + Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0])); + Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1])); + Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2])); + Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3])); + Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4])); + Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5])); + Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6])); + Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7])); + Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8])); + Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9])); Assert.That(Thread.ThreadState.V10, Is.EqualTo(UnicornEmu.Q[10])); Assert.That(Thread.ThreadState.V11, Is.EqualTo(UnicornEmu.Q[11])); Assert.That(Thread.ThreadState.V12, Is.EqualTo(UnicornEmu.Q[12])); @@ -238,11 +252,13 @@ namespace Ryujinx.Tests.Cpu Assert.That(Thread.ThreadState.V30, Is.EqualTo(UnicornEmu.Q[30])); Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31])); Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31])); - Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr)); - Assert.That(Thread.ThreadState.Fpsr & 0x08000000, Is.EqualTo(UnicornEmu.Fpsr & 0x08000000)); + + Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr)); + Assert.That(Thread.ThreadState.Fpsr & FpsrMask, Is.EqualTo(UnicornEmu.Fpsr & FpsrMask)); + Assert.That(Thread.ThreadState.Overflow, Is.EqualTo(UnicornEmu.OverflowFlag)); - Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag)); - Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag)); + Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag)); + Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag)); Assert.That(Thread.ThreadState.Negative, Is.EqualTo(UnicornEmu.NegativeFlag)); } diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index 3a47dbee69..43952d195b 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -1,4 +1,4 @@ -//#define Alu +#define Alu using ChocolArm64.State; @@ -6,334 +6,185 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Alu"), Ignore("Tested: second half of 2018.")] + [Category("Alu")] // Tested: second half of 2018. public sealed class CpuTestAlu : CpuTest { #if Alu - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("CLS , ")] + [Test, Pairwise, Description("CLS , ")] public void Cls_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC01400; // CLS X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Cls(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("CLS , ")] + [Test, Pairwise, Description("CLS , ")] public void Cls_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC01400; // CLS W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Cls(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } + CompareAgainstUnicorn(); } - [Test, Description("CLZ , ")] + [Test, Pairwise, Description("CLZ , ")] public void Clz_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC01000; // CLZ X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Clz(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("CLZ , ")] + [Test, Pairwise, Description("CLZ , ")] public void Clz_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC01000; // CLZ W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Clz(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("RBIT , ")] + [Test, Pairwise, Description("RBIT , ")] public void Rbit_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00000; // RBIT X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rbit(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("RBIT , ")] + [Test, Pairwise, Description("RBIT , ")] public void Rbit_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC00000; // RBIT W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Rbit(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV16 , ")] + [Test, Pairwise, Description("REV16 , ")] public void Rev16_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00400; // REV16 X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rev16(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV16 , ")] + [Test, Pairwise, Description("REV16 , ")] public void Rev16_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC00400; // REV16 W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Rev16(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV32 , ")] + [Test, Pairwise, Description("REV32 , ")] public void Rev32_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00800; // REV32 X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rev32(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV , ")] + [Test, Pairwise, Description("REV , ")] public void Rev32_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC00800; // REV W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Rev32(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV64 , ")] + [Test, Pairwise, Description("REV64 , ")] public void Rev64_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00C00; // REV64 X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rev64(Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs index b648a337e3..61eadefd35 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs @@ -1,4 +1,4 @@ -//#define AluImm +#define AluImm using ChocolArm64.State; @@ -6,824 +6,448 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("AluImm"), Ignore("Tested: second half of 2018.")] + [Category("AluImm")] // Tested: second half of 2018. public sealed class CpuTestAluImm : CpuTest { #if AluImm - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntImm = 2; + private const int RndCntImms = 2; + private const int RndCntImmr = 2; - [Test, Description("ADD , , #{, }")] + [Test, Pairwise, Description("ADD , , #{, }")] public void Add_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , #{, }")] + [Test, Pairwise, Description("ADD , , #{, }")] public void Add_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x11000000; // ADD W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADDS , , #{, }")] + [Test, Pairwise, Description("ADDS , , #{, }")] public void Adds_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , #{, }")] + [Test, Pairwise, Description("ADDS , , #{, }")] public void Adds_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("AND , , #")] + [Test, Pairwise, Description("AND , , #")] public void And_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0x92400000; // AND X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("AND , , #")] + [Test, Pairwise, Description("AND , , #")] public void And_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x92000000; // AND X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("AND , , #")] + [Test, Pairwise, Description("AND , , #")] public void And_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x12000000; // AND W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ANDS , , #")] + [Test, Pairwise, Description("ANDS , , #")] public void Ands_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ANDS , , #")] + [Test, Pairwise, Description("ANDS , , #")] public void Ands_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0xF2000000; // ANDS X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ANDS , , #")] + [Test, Pairwise, Description("ANDS , , #")] public void Ands_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x72000000; // ANDS W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("EOR , , #")] + [Test, Pairwise, Description("EOR , , #")] public void Eor_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0xD2400000; // EOR X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , #")] + [Test, Pairwise, Description("EOR , , #")] public void Eor_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0xD2000000; // EOR X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , #")] + [Test, Pairwise, Description("EOR , , #")] public void Eor_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x52000000; // EOR W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , #")] + [Test, Pairwise, Description("ORR , , #")] public void Orr_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0xB2400000; // ORR X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , #")] + [Test, Pairwise, Description("ORR , , #")] public void Orr_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , #")] + [Test, Pairwise, Description("ORR , , #")] public void Orr_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x32000000; // ORR W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , #{, }")] + [Test, Pairwise, Description("SUB , , #{, }")] public void Sub_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , #{, }")] + [Test, Pairwise, Description("SUB , , #{, }")] public void Sub_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUBS , , #{, }")] + [Test, Pairwise, Description("SUBS , , #{, }")] public void Subs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , #{, }")] + [Test, Pairwise, Description("SUBS , , #{, }")] public void Subs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs index 49c82b7425..58a99dfb18 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs @@ -1,4 +1,4 @@ -//#define AluRs +#define AluRs using ChocolArm64.State; @@ -6,1958 +6,1117 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("AluRs"), Ignore("Tested: second half of 2018.")] + [Category("AluRs")] // Tested: second half of 2018. public sealed class CpuTestAluRs : CpuTest { #if AluRs - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntAmount = 2; + private const int RndCntLsb = 2; - [Test, Description("ADC , , ")] + [Test, Pairwise, Description("ADC , , ")] public void Adc_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0x9A000000; // ADC X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ADC , , ")] + [Test, Pairwise, Description("ADC , , ")] public void Adc_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x1A000000; // ADC W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ADCS , , ")] + [Test, Pairwise, Description("ADCS , , ")] public void Adcs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0xBA000000; // ADCS X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADCS , , ")] + [Test, Pairwise, Description("ADCS , , ")] public void Adcs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x3A000000; // ADCS W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, #}")] + [Test, Pairwise, Description("ADD , , {, #}")] public void Add_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0x8B000000; // ADD X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Add_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, #}")] + [Test, Pairwise, Description("ADD , , {, #}")] public void Add_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x0B000000; // ADD W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - CompareAgainstUnicorn(); - } + CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, #}")] + [Test, Pairwise, Description("ADDS , , {, #}")] public void Adds_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xAB000000; // ADDS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Adds_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, #}")] + [Test, Pairwise, Description("ADDS , , {, #}")] public void Adds_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x2B000000; // ADDS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Adds_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("AND , , {, #}")] + [Test, Pairwise, Description("AND , , {, #}")] public void And_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0x8A000000; // AND X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.And_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("AND , , {, #}")] + [Test, Pairwise, Description("AND , , {, #}")] public void And_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x0A000000; // AND W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.And_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ANDS , , {, #}")] + [Test, Pairwise, Description("ANDS , , {, #}")] public void Ands_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xEA000000; // ANDS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Ands_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ANDS , , {, #}")] + [Test, Pairwise, Description("ANDS , , {, #}")] public void Ands_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x6A000000; // ANDS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Ands_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ASRV , , ")] + [Test, Pairwise, Description("ASRV , , ")] public void Asrv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02800; // ASRV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Asrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ASRV , , ")] + [Test, Pairwise, Description("ASRV , , ")] public void Asrv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02800; // ASRV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Asrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("BIC , , {, #}")] + [Test, Pairwise, Description("BIC , , {, #}")] public void Bic_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0x8A200000; // BIC X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Bic(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("BIC , , {, #}")] + [Test, Pairwise, Description("BIC , , {, #}")] public void Bic_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x0A200000; // BIC W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Bic(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("BICS , , {, #}")] + [Test, Pairwise, Description("BICS , , {, #}")] public void Bics_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xEA200000; // BICS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Bics(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("BICS , , {, #}")] + [Test, Pairwise, Description("BICS , , {, #}")] public void Bics_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x6A200000; // BICS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Bics(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CRC32X , , ")] + [Test, Pairwise, Description("CRC32X , , "), Ignore("Unicorn fails.")] public void Crc32x([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ulong)0x00_00_00_00_00_00_00_00, (ulong)0x7F_FF_FF_FF_FF_FF_FF_FF, (ulong)0x80_00_00_00_00_00_00_00, - (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(64)] ulong Xm) + (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC04C00; // CRC32X W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Xm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32W , , ")] + [Test, Pairwise, Description("CRC32W , , "), Ignore("Unicorn fails.")] public void Crc32w([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF, - (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(64)] uint Wm) + (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC04800; // CRC32W W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32H , , ")] + [Test, Pairwise, Description("CRC32H , , "), Ignore("Unicorn fails.")] public void Crc32h([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ushort)0x00_00, (ushort)0x7F_FF, - (ushort)0x80_00, (ushort)0xFF_FF)] [Random(64)] ushort Wm) + (ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort Wm) { uint Opcode = 0x1AC04400; // CRC32H W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32B , , ")] + [Test, Pairwise, Description("CRC32B , , "), Ignore("Unicorn fails.")] public void Crc32b([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(64)] byte Wm) + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm) { uint Opcode = 0x1AC04000; // CRC32B W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CX , , ")] + [Test, Pairwise, Description("CRC32CX , , ")] public void Crc32cx([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ulong)0x00_00_00_00_00_00_00_00, (ulong)0x7F_FF_FF_FF_FF_FF_FF_FF, (ulong)0x80_00_00_00_00_00_00_00, - (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(64)] ulong Xm) + (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC05C00; // CRC32CX W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Xm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CW , , ")] + [Test, Pairwise, Description("CRC32CW , , ")] public void Crc32cw([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF, - (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(64)] uint Wm) + (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC05800; // CRC32CW W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CH , , ")] + [Test, Pairwise, Description("CRC32CH , , ")] public void Crc32ch([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ushort)0x00_00, (ushort)0x7F_FF, - (ushort)0x80_00, (ushort)0xFF_FF)] [Random(64)] ushort Wm) + (ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort Wm) { uint Opcode = 0x1AC05400; // CRC32CH W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CB , , ")] + [Test, Pairwise, Description("CRC32CB , , ")] public void Crc32cb([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(64)] byte Wm) + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm) { uint Opcode = 0x1AC05000; // CRC32CB W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("EON , , {, #}")] + [Test, Pairwise, Description("EON , , {, #}")] public void Eon_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xCA200000; // EON X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Eon(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("EON , , {, #}")] + [Test, Pairwise, Description("EON , , {, #}")] public void Eon_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x4A200000; // EON W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Eon(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , {, #}")] + [Test, Pairwise, Description("EOR , , {, #}")] public void Eor_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xCA000000; // EOR X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Eor_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , {, #}")] + [Test, Pairwise, Description("EOR , , {, #}")] public void Eor_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x4A000000; // EOR W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Eor_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("EXTR , , , #")] + [Test, Pairwise, Description("EXTR , , , #")] public void Extr_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint lsb) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntLsb)] uint lsb) { uint Opcode = 0x93C00000; // EXTR X0, X0, X0, #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((lsb & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Extr(Op[31], Op[22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("EXTR , , , #")] + [Test, Pairwise, Description("EXTR , , , #")] public void Extr_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint lsb) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntLsb)] uint lsb) { uint Opcode = 0x13800000; // EXTR W0, W0, W0, #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((lsb & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Extr(Op[31], Op[22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSLV , , ")] + [Test, Pairwise, Description("LSLV , , ")] public void Lslv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02000; // LSLV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Lslv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSLV , , ")] + [Test, Pairwise, Description("LSLV , , ")] public void Lslv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02000; // LSLV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Lslv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSRV , , ")] + [Test, Pairwise, Description("LSRV , , ")] public void Lsrv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02400; // LSRV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Lsrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSRV , , ")] + [Test, Pairwise, Description("LSRV , , ")] public void Lsrv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02400; // LSRV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Lsrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORN , , {, #}")] + [Test, Pairwise, Description("ORN , , {, #}")] public void Orn_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xAA200000; // ORN X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Orn(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORN , , {, #}")] + [Test, Pairwise, Description("ORN , , {, #}")] public void Orn_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x2A200000; // ORN W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Orn(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , {, #}")] + [Test, Pairwise, Description("ORR , , {, #}")] public void Orr_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xAA000000; // ORR X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Orr_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , {, #}")] + [Test, Pairwise, Description("ORR , , {, #}")] public void Orr_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x2A000000; // ORR W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Orr_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("RORV , , ")] + [Test, Pairwise, Description("RORV , , ")] public void Rorv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02C00; // RORV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Rorv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("RORV , , ")] + [Test, Pairwise, Description("RORV , , ")] public void Rorv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02C00; // RORV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Rorv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBC , , ")] + [Test, Pairwise, Description("SBC , , ")] public void Sbc_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0xDA000000; // SBC X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Sbc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBC , , ")] + [Test, Pairwise, Description("SBC , , ")] public void Sbc_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x5A000000; // SBC W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Sbc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBCS , , ")] + [Test, Pairwise, Description("SBCS , , ")] public void Sbcs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0xFA000000; // SBCS X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Sbcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SBCS , , ")] + [Test, Pairwise, Description("SBCS , , ")] public void Sbcs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x7A000000; // SBCS W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Sbcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SDIV , , ")] + [Test, Pairwise, Description("SDIV , , ")] public void Sdiv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC00C00; // SDIV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Sdiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SDIV , , ")] + [Test, Pairwise, Description("SDIV , , ")] public void Sdiv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC00C00; // SDIV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sdiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, #}")] + [Test, Pairwise, Description("SUB , , {, #}")] public void Sub_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xCB000000; // SUB X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Sub_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, #}")] + [Test, Pairwise, Description("SUB , , {, #}")] public void Sub_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x4B000000; // SUB W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, #}")] + [Test, Pairwise, Description("SUBS , , {, #}")] public void Subs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xEB000000; // SUBS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Subs_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, #}")] + [Test, Pairwise, Description("SUBS , , {, #}")] public void Subs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x6B000000; // SUBS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Subs_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("UDIV , , ")] + [Test, Pairwise, Description("UDIV , , ")] public void Udiv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC00800; // UDIV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Udiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UDIV , , ")] + [Test, Pairwise, Description("UDIV , , ")] public void Udiv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC00800; // UDIV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Udiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs index 41fd580a6f..9c66532b9a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs @@ -1,4 +1,4 @@ -//#define AluRx +#define AluRx using ChocolArm64.State; @@ -6,77 +6,51 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("AluRx"), Ignore("Tested: second half of 2018.")] + [Category("AluRx")] // Tested: second half of 2018. public sealed class CpuTestAluRx : CpuTest { #if AluRx - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0x8B206000; // ADD X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Xm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Xm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -84,50 +58,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -135,50 +90,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -186,50 +122,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -237,50 +154,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -288,50 +186,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -339,95 +218,51 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0xAB206000; // ADDS X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -435,45 +270,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -481,45 +291,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -527,45 +312,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -573,45 +333,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -619,45 +354,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -665,95 +375,51 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0xCB206000; // SUB X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Xm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Xm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -761,50 +427,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -812,50 +459,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -863,50 +491,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -914,50 +523,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -965,50 +555,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1016,95 +587,51 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0xEB206000; // SUBS X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1112,45 +639,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1158,45 +660,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1204,45 +681,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1250,45 +702,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1296,45 +723,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1342,34 +744,9 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs index c5be578850..427396f8be 100644 --- a/Ryujinx.Tests/Cpu/CpuTestBfm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs @@ -1,4 +1,4 @@ -//#define Bfm +#define Bfm using ChocolArm64.State; @@ -6,212 +6,127 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Bfm"), Ignore("Tested: second half of 2018.")] + [Category("Bfm")] // Tested: second half of 2018. public sealed class CpuTestBfm : CpuTest { #if Bfm - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntImmr = 2; + private const int RndCntImms = 2; - [Test, Description("BFM , , #, #")] + [Test, Pairwise, Description("BFM , , #, #")] public void Bfm_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, - [Random(2)] ulong _Xd, + [Random(RndCnt)] ulong _Xd, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) { uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Xd)); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("BFM , , #, #")] + [Test, Pairwise, Description("BFM , , #, #")] public void Bfm_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, - [Random(2)] uint _Wd, + [Random(RndCnt)] uint _Wd, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) { uint Opcode = 0x33000000; // BFM W0, W0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Wd)); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBFM , , #, #")] + [Test, Pairwise, Description("SBFM , , #, #")] public void Sbfm_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) { uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBFM , , #, #")] + [Test, Pairwise, Description("SBFM , , #, #")] public void Sbfm_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) { uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("UBFM , , #, #")] + [Test, Pairwise, Description("UBFM , , #, #")] public void Ubfm_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) { uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UBFM , , #, #")] + [Test, Pairwise, Description("UBFM , , #, #")] public void Ubfm_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) { uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs index 245b04c0a1..7ca92d4fea 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs @@ -1,4 +1,4 @@ -//#define CcmpImm +#define CcmpImm using ChocolArm64.State; @@ -6,25 +6,20 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("CcmpImm"), Ignore("Tested: second half of 2018.")] + [Category("CcmpImm")] // Tested: second half of 2018. public sealed class CpuTestCcmpImm : CpuTest { #if CcmpImm - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntImm = 2; + private const int RndCntNzcv = 2; - [Test, Description("CCMN , #, #, ")] + [Test, Pairwise, Description("CCMN , #, #, ")] public void Ccmn_64bit([Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMN , #, #, ")] + [Test, Pairwise, Description("CCMN , #, #, ")] public void Ccmn_32bit([Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , #, #, ")] + [Test, Pairwise, Description("CCMP , #, #, ")] public void Ccmp_64bit([Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , #, #, ")] + [Test, Pairwise, Description("CCMP , #, #, ")] public void Ccmp_32bit([Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs index 8c4e503ee9..36120f7409 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs @@ -1,4 +1,4 @@ -//#define CcmpReg +#define CcmpReg using ChocolArm64.State; @@ -6,27 +6,21 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("CcmpReg"), Ignore("Tested: second half of 2018.")] + [Category("CcmpReg")] // Tested: second half of 2018. public sealed class CpuTestCcmpReg : CpuTest { #if CcmpReg - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntNzcv = 2; - [Test, Description("CCMN , , #, ")] + [Test, Pairwise, Description("CCMN , , #, ")] public void Ccmn_64bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMN , , #, ")] + [Test, Pairwise, Description("CCMN , , #, ")] public void Ccmn_32bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , , #, ")] + [Test, Pairwise, Description("CCMP , , #, ")] public void Ccmp_64bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , , #, ")] + [Test, Pairwise, Description("CCMP , , #, ")] public void Ccmp_32bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/Ryujinx.Tests/Cpu/CpuTestCsel.cs index d532a12c69..2d88b9f033 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCsel.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCsel.cs @@ -1,4 +1,4 @@ -//#define Csel +#define Csel using ChocolArm64.State; @@ -6,27 +6,20 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Csel"), Ignore("Tested: second half of 2018.")] + [Category("Csel")] // Tested: second half of 2018. public sealed class CpuTestCsel : CpuTest { #if Csel - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("CSEL , , , ")] + [Test, Pairwise, Description("CSEL , , , ")] public void Csel_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSEL , , , ")] public void Csel_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINC , , , ")] public void Csinc_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINC , , , ")] public void Csinc_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINV , , , ")] public void Csinv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINV , , , ")] public void Csinv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSNEG , , , ")] public void Csneg_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSNEG , , , ")] public void Csneg_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , #{, LSL #}")] + [Test, Pairwise, Description("MOVK , #{, LSL #}")] public void Movk_64bit([Values(0u, 31u)] uint Rd, - [Random(12)] ulong _Xd, - [Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm, + [Random(RndCntImm)] ulong _Xd, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u, 32u, 48u)] uint shift) { uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0 @@ -30,29 +23,16 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Xd)); - Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVK , #{, LSL #}")] + [Test, Pairwise, Description("MOVK , #{, LSL #}")] public void Movk_32bit([Values(0u, 31u)] uint Rd, - [Random(12)] uint _Wd, - [Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm, + [Random(RndCntImm)] uint _Wd, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u)] uint shift) { uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0 @@ -60,28 +40,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Wd)); - Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVN , #{, LSL #}")] + [Test, Pairwise, Description("MOVN , #{, LSL #}")] public void Movn_64bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u, 32u, 48u)] uint shift) { uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0 @@ -89,27 +56,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVN , #{, LSL #}")] + [Test, Pairwise, Description("MOVN , #{, LSL #}")] public void Movn_32bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u)] uint shift) { uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0 @@ -117,27 +72,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVZ , #{, LSL #}")] + [Test, Pairwise, Description("MOVZ , #{, LSL #}")] public void Movz_64bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u, 32u, 48u)] uint shift) { uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0 @@ -145,27 +88,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVZ , #{, LSL #}")] + [Test, Pairwise, Description("MOVZ , #{, LSL #}")] public void Movz_32bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u)] uint shift) { uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0 @@ -173,21 +104,9 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestMul.cs b/Ryujinx.Tests/Cpu/CpuTestMul.cs index 2e8aa76fa0..056c45437a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestMul.cs +++ b/Ryujinx.Tests/Cpu/CpuTestMul.cs @@ -1,4 +1,4 @@ -//#define Mul +#define Mul using ChocolArm64.State; @@ -6,378 +6,223 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Mul"), Ignore("Tested: second half of 2018.")] + [Category("Mul")] // Tested: second half of 2018. public sealed class CpuTestMul : CpuTest { #if Mul - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("MADD , , , ")] + [Test, Pairwise, Description("MADD , , , ")] public void Madd_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B000000; // MADD X0, X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MADD , , , ")] + [Test, Pairwise, Description("MADD , , , ")] public void Madd_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa) { uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Wa)); - Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("MSUB , , , ")] + [Test, Pairwise, Description("MSUB , , , ")] public void Msub_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MSUB , , , ")] + [Test, Pairwise, Description("MSUB , , , ")] public void Msub_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa) { uint Opcode = 0x1B008000; // MSUB W0, W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Wa)); - Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SMADDL , , , ")] + [Test, Pairwise, Description("SMADDL , , , ")] public void Smaddl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B200000; // SMADDL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Smaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UMADDL , , , ")] + [Test, Pairwise, Description("UMADDL , , , ")] public void Umaddl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Umaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SMSUBL , , , ")] + [Test, Pairwise, Description("SMSUBL , , , ")] public void Smsubl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Smsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UMSUBL , , , ")] + [Test, Pairwise, Description("UMSUBL , , , ")] public void Umsubl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Umsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SMULH , , ")] + [Test, Pairwise, Description("SMULH , , ")] public void Smulh_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9B407C00; // SMULH X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Smulh(Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UMULH , , ")] + [Test, Pairwise, Description("UMULH , , ")] public void Umulh_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Umulh(Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 37fb3e9769..c710540da6 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -8,18 +8,10 @@ using System.Runtime.Intrinsics; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Simd")/*, Ignore("Tested: second half of 2018.")*/] + [Category("Simd")] // Tested: second half of 2018. public sealed class CpuTestSimd : CpuTest { #if Simd - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } #region "ValueSource" private static ulong[] _1B1H1S1D_() @@ -156,7 +148,7 @@ namespace Ryujinx.Tests.Cpu } #endregion - private const int RndCnt = 4; + private const int RndCnt = 2; [Test, Pairwise, Description("ABS , ")] public void Abs_S_D([Values(0u)] uint Rd, @@ -166,21 +158,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE0B800; // ABS D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Abs_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -194,21 +177,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20B800; // ABS V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -222,21 +196,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20B800; // ABS V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -248,21 +213,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EF1B800; // ADDP D0, V0.2D Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Addp_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -276,21 +232,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E31B800; // ADDV B0, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -304,21 +251,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E31B800; // ADDV B0, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -332,21 +270,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E204800; // CLS V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -360,21 +289,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E204800; // CLS V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -388,21 +308,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E204800; // CLZ V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -416,21 +327,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E204800; // CLZ V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -442,21 +344,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE09800; // CMEQ D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmeq_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -470,21 +363,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E209800; // CMEQ V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmeq_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -498,21 +382,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E209800; // CMEQ V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmeq_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -524,21 +399,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE08800; // CMGE D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmge_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -552,21 +418,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208800; // CMGE V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmge_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -580,21 +437,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208800; // CMGE V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmge_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -606,21 +454,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE08800; // CMGT D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmgt_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -634,21 +473,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208800; // CMGT V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmgt_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -662,21 +492,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208800; // CMGT V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmgt_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -688,21 +509,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE09800; // CMLE D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmle_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -716,21 +528,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E209800; // CMLE V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmle_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -744,21 +547,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E209800; // CMLE V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmle_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -770,21 +564,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE0A800; // CMLT D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmlt_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -798,21 +583,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20A800; // CMLT V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmlt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -826,21 +602,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20A800; // CMLT V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmlt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -852,21 +619,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E205800; // CNT V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -878,21 +636,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E205800; // CNT V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -904,37 +653,17 @@ namespace Ryujinx.Tests.Cpu { //const int FZFlagBit = 24; // Flush-to-zero mode control bit. - //const int IDCFlagBit = 7; // Input Denormal cumulative floating-point exception bit. - //const int IXCFlagBit = 4; // Inexact cumulative floating-point exception bit. - //const int IOCFlagBit = 0; // Invalid Operation cumulative floating-point exception bit. - uint Opcode = 0x5E21A800; // FCVTNS S0, S0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - //Shared.FPCR = new Bits((uint)Fpcr); - SimdFp.Fcvtns_S(Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - /*Assert.Multiple(() => - { - Assert.That(((ThreadState.Fpsr >> IDCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IDCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IXCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IXCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IOCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IOCFlagBit])); - });*/ + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNS , ")] @@ -945,21 +674,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E61A800; // FCVTNS D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Fcvtns_S(Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNS ., .")] @@ -972,21 +693,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E21A800; // FCVTNS V0.2S, V0.2S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((Q & 1) << 30); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A * Q); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A * Q)); - SimdFp.Fcvtns_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNS ., .")] @@ -997,21 +710,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E61A800; // FCVTNS V0.2D, V0.2D Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Fcvtns_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNU , ")] @@ -1022,37 +727,17 @@ namespace Ryujinx.Tests.Cpu { //const int FZFlagBit = 24; // Flush-to-zero mode control bit. - //const int IDCFlagBit = 7; // Input Denormal cumulative floating-point exception bit. - //const int IXCFlagBit = 4; // Inexact cumulative floating-point exception bit. - //const int IOCFlagBit = 0; // Invalid Operation cumulative floating-point exception bit. - uint Opcode = 0x7E21A800; // FCVTNU S0, S0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - //Shared.FPCR = new Bits((uint)Fpcr); - SimdFp.Fcvtnu_S(Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - /*Assert.Multiple(() => - { - Assert.That(((ThreadState.Fpsr >> IDCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IDCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IXCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IXCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IOCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IOCFlagBit])); - });*/ + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNU , ")] @@ -1063,21 +748,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7E61A800; // FCVTNU D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Fcvtnu_S(Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNU ., .")] @@ -1090,21 +767,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E21A800; // FCVTNU V0.2S, V0.2S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((Q & 1) << 30); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A * Q); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A * Q)); - SimdFp.Fcvtnu_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("FCVTNU ., .")] @@ -1115,21 +784,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E61A800; // FCVTNU V0.2D, V0.2D Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Fcvtnu_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("NEG , ")] @@ -1140,21 +801,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE0B800; // NEG D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Neg_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1168,21 +820,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E20B800; // NEG V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1196,21 +839,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E20B800; // NEG V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1222,21 +856,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E205800; // NOT V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Not_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1248,21 +873,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E205800; // NOT V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Not_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1274,21 +890,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E605800; // RBIT V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1300,21 +907,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E605800; // RBIT V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1326,21 +924,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E201800; // REV16 V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1352,21 +941,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E201800; // REV16 V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1380,21 +960,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E200800; // REV32 V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1408,21 +979,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E200800; // REV32 V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1436,21 +998,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E200800; // REV64 V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1464,21 +1017,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E200800; // REV64 V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1492,21 +1036,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E206800; // SADALP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1520,21 +1055,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E206800; // SADALP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1548,21 +1074,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E202800; // SADDLP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1576,21 +1093,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E202800; // SADDLP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1602,26 +1110,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - SimdFp.Sha256su0_V(Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1632,27 +1126,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E207800; // SQABS B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqabs_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1663,27 +1145,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E207800; // SQABS V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1694,27 +1164,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E207800; // SQABS V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1725,27 +1183,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E207800; // SQNEG B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqneg_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1756,27 +1202,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E207800; // SQNEG V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1787,27 +1221,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E207800; // SQNEG V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1818,27 +1240,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E214800; // SQXTN B0, H0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1849,27 +1259,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E214800; // SQXTN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1880,27 +1278,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E214800; // SQXTN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1911,27 +1297,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E212800; // SQXTUN B0, H0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1942,27 +1316,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E212800; // SQXTUN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -1973,27 +1335,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E212800; // SQXTUN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2004,27 +1354,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E203800; // SUQADD B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Suqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2035,27 +1373,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E203800; // SUQADD V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2066,27 +1392,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E203800; // SUQADD V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2100,21 +1414,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E206800; // UADALP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2128,21 +1433,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E206800; // UADALP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2156,21 +1452,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E202800; // UADDLP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2184,21 +1471,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E202800; // UADDLP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2209,27 +1487,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E214800; // UQXTN B0, H0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Uqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2240,27 +1506,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E214800; // UQXTN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2271,27 +1525,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E214800; // UQXTN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2302,27 +1544,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E203800; // USQADD B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Usqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2333,27 +1563,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E203800; // USQADD V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2364,27 +1582,15 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E203800; // USQADD V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); CompareAgainstUnicorn(); } @@ -2398,21 +1604,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E212800; // XTN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2426,21 +1623,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E212800; // XTN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index e9fd462ebc..d3b6c79ee3 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestSimdArithmetic : CpuTest { - [TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] // FMAX S0, S1, S2 [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] [TestCase(0x1E224820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x000000003DCCCCCDul)] @@ -22,17 +22,19 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)] [TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)] [TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)] - [TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)] + [TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)] // FMAX D0, D1, D2 [TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] [TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] [TestCase(0x1E624820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x3FF3333333333333ul)] public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result) { - // FMAX S0, S1, S2 - AThreadState ThreadState = SingleOpcode(Opcode, - V1: Sse.StaticCast(Sse2.SetVector128(0, A)), - V2: Sse.StaticCast(Sse2.SetVector128(0, B))); - Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast(ThreadState.V0), 0)); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } @@ -51,19 +53,23 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)] public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1) { - uint Opcode = 0x4E22F420; + uint Opcode = 0x4E22F420; // FMAX V0.4S, V1.4S, V2.4S + Vector128 V1 = MakeVectorE0E1(A, B); Vector128 V2 = MakeVectorE0E1(C, D); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } - [TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] + [TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] // FMIN S0, S1, S2 [TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000080000000ul)] [TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] [TestCase(0x1E225820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x0000000080000000ul)] @@ -76,17 +82,19 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)] [TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)] [TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)] - [TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] + [TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] // FMIN D0, D1, D2 [TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)] [TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] [TestCase(0x1E625820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x8000000000000000ul)] public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result) { - // FMIN S0, S1, S2 - AThreadState ThreadState = SingleOpcode(Opcode, - V1: Sse.StaticCast(Sse2.SetVector128(0, A)), - V2: Sse.StaticCast(Sse2.SetVector128(0, B))); - Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast(ThreadState.V0), 0)); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } @@ -105,15 +113,19 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)] public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1) { - uint Opcode = 0x4EA2F420; + uint Opcode = 0x4EA2F420; // FMIN V0.4S, V1.4S, V2.4S + Vector128 V1 = MakeVectorE0E1(A, B); Vector128 V2 = MakeVectorE0E1(C, D); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -125,6 +137,7 @@ namespace Ryujinx.Tests.Cpu V0: Sse.SetVector128(0, B, 0, 0)); Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B)); + CompareAgainstUnicorn(); } @@ -137,13 +150,18 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x007FF000u, 0x7E800000u)] public void Frecpe_S(uint A, uint Result) { + uint Opcode = 0x5EA1D820; // FRECPE S0, S1 + Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x5EA1D820, V1: V1); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [Test, Description("FRECPS D0, D1, D2")] + [Test, Description("FRECPS D0, D1, D2"), Ignore("Not accurate enough.")] public void Frecps_S([Random(10)] double A, [Random(10)] double B) { AThreadState ThreadState = SingleOpcode(0x5E62FC20, @@ -151,7 +169,8 @@ namespace Ryujinx.Tests.Cpu V2: MakeVectorE0(B)); Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B))); - //CompareAgainstUnicorn(); // Not accurate enough + + CompareAgainstUnicorn(); } [Test, Description("FRECPS V4.4S, V2.4S, V0.4S")] @@ -170,6 +189,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(Result)); Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(Result)); }); + CompareAgainstUnicorn(); } @@ -213,42 +233,53 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frinta_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E264020; // FRINTA S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [Ignore("Wrong opcodes.")] + [TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTA V0.2D, V1.2D [TestCase(0x6E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)] + [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)] // FRINTX V0.4S, V1.4S [TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)] + [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)] // FRINTX V0.2S, V1.2S [TestCase(0x2E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] // FRINTA V0.2S, V1.2S [TestCase(0x2E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] [TestCase(0x2E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] [TestCase(0x2E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frinta_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -294,36 +325,31 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, 'Z', true, 0x7FC00000u, Ignore = "NaN test.")] public void Frinti_S(uint A, char RoundType, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E27C020; // FRINTI S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E27C020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTI V0.2D, V1.2D [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'N', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] @@ -331,11 +357,11 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'M', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] - [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)] + [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)] // FRINTI V0.4S, V1.4S [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)] [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)] + [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)] // FRINTI V0.2S, V1.2S [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)] [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] @@ -357,36 +383,29 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x2EA19820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, 'Z', true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frinti_V(uint Opcode, ulong A, ulong B, char RoundType, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -430,42 +449,53 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintm_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E254020; // FRINTM S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E254020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTM V0.2D, V1.2D [TestCase(0x4E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] - [TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)] - [TestCase(0xE219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] - [TestCase(0xE219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] - [TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] - [TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] // FRINTM V0.4S, V1.4S + [TestCase(0x0E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)] // FRINTM V0.2S, V1.2S + [TestCase(0x0E219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x0E219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] + [TestCase(0x0E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintm_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } + [Ignore("Wrong opcode.")] [TestCase(0x3FE66666u, false, 0x40000000u)] [TestCase(0x3F99999Au, false, 0x3F800000u)] [TestCase(0x404CCCCDu, false, 0x40400000u)] @@ -506,42 +536,52 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintn_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E264020; // FRINTA S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTN V0.2D, V1.2D [TestCase(0x4E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x4E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] - [TestCase(0x4E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)] + [TestCase(0x4E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)] // FRINTN V0.4S, V1.4S [TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] - [TestCase(0xE218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)] // FRINTN V0.2S, V1.2S + [TestCase(0x0E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] + [TestCase(0x0E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x0E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] + [TestCase(0x0E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintn_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -585,39 +625,49 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintp_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E24C020; // FRINTP S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E24C020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] + [TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] // FRINTP V0.2D, v1.2D [TestCase(0x4EE18820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)] - [TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0xEA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] - [TestCase(0xEA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] - [TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] - [TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] // FRINTP V0.4S, v1.4S + [TestCase(0x0EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] // FRINTP V0.2S, v1.2S + [TestCase(0x0EA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x0EA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] + [TestCase(0x0EA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0EA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintp_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -663,36 +713,31 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, 'Z', true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintx_S(uint A, char RoundType, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E274020; // FRINTX S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTX V0.2D, V1.2D [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'N', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] @@ -700,11 +745,11 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'M', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)] + [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)] // FRINTX V0.4S, V1.4S [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)] [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)] + [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)] // FRINTX V0.2S, V1.2S [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)] [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] @@ -726,45 +771,43 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x2E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, 'Z', true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintx_V(uint Opcode, ulong A, ulong B, char RoundType, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } [TestCase(0x41200000u, 0x3EA18000u)] public void Frsqrte_S(uint A, uint Result) { + uint Opcode = 0x7EA1D820; // FRSQRTE S0, S1 + Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x7EA1D820, V1: V1); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs index acf7000b9a..a1558b05af 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs @@ -24,12 +24,15 @@ namespace Ryujinx.Tests.Cpu } #endregion + private const int RndCnt = 2; + [Test, Description("FCMEQ D0, D1, D2 | FCMGE D0, D1, D2 | FCMGT D0, D1, D2")] - public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(8)] double A, - [ValueSource("_doubles_")] [Random(8)] double B, + public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(RndCnt)] double A, + [ValueSource("_doubles_")] [Random(RndCnt)] double B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x5E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble())); Vector128 V1 = Sse.StaticCast(Sse2.SetScalarVector128(A)); Vector128 V2 = Sse.StaticCast(Sse2.SetScalarVector128(B)); @@ -52,15 +55,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ S0, S1, S2 | FCMGE S0, S1, S2 | FCMGT S0, S1, S2")] - public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(8)] float A, - [ValueSource("_floats_")] [Random(8)] float B, + public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(RndCnt)] float A, + [ValueSource("_floats_")] [Random(RndCnt)] float B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x5E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetScalarVector128(A); Vector128 V2 = Sse.SetScalarVector128(B); @@ -85,15 +90,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ V0.2D, V1.2D, V2.2D | FCMGE V0.2D, V1.2D, V2.2D | FCMGT V0.2D, V1.2D, V2.2D")] - public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(8)] double A, - [ValueSource("_doubles_")] [Random(8)] double B, + public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(RndCnt)] double A, + [ValueSource("_doubles_")] [Random(RndCnt)] double B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x4E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V1 = Sse.StaticCast(Sse2.SetAllVector128(A)); Vector128 V2 = Sse.StaticCast(Sse2.SetAllVector128(B)); @@ -115,15 +122,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ V0.2S, V1.2S, V2.2S | FCMGE V0.2S, V1.2S, V2.2S | FCMGT V0.2S, V1.2S, V2.2S")] - public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(8)] float A, - [ValueSource("_floats_")] [Random(8)] float B, + public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(RndCnt)] float A, + [ValueSource("_floats_")] [Random(RndCnt)] float B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x0E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetVector128(0, 0, A, A); Vector128 V2 = Sse.SetVector128(0, 0, B, B); @@ -148,15 +157,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ V0.4S, V1.4S, V2.4S | FCMGE V0.4S, V1.4S, V2.4S | FCMGT V0.4S, V1.4S, V2.4S")] - public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(8)] float A, - [ValueSource("_floats_")] [Random(8)] float B, + public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(RndCnt)] float A, + [ValueSource("_floats_")] [Random(RndCnt)] float B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x4E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V1 = Sse.SetAllVector128(A); Vector128 V2 = Sse.SetAllVector128(B); @@ -180,15 +191,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT D0, D1, #0.0 | FCMGE D0, D1, #0.0 | FCMEQ D0, D1, #0.0 | FCMLE D0, D1, #0.0 | FCMLT D0, D1, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(8)] double A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(RndCnt)] double A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x5EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble())); Vector128 V1 = Sse.StaticCast(Sse2.SetScalarVector128(A)); @@ -219,15 +232,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT S0, S1, #0.0 | FCMGE S0, S1, #0.0 | FCMEQ S0, S1, #0.0 | FCMLE S0, S1, #0.0 | FCMLT S0, S1, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(8)] float A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(RndCnt)] float A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x5EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetScalarVector128(A); @@ -260,15 +275,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT V0.2D, V1.2D, #0.0 | FCMGE V0.2D, V1.2D, #0.0 | FCMEQ V0.2D, V1.2D, #0.0 | FCMLE V0.2D, V1.2D, #0.0 | FCMLT V0.2D, V1.2D, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(8)] double A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(RndCnt)] double A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x4EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V1 = Sse.StaticCast(Sse2.SetAllVector128(A)); AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); @@ -298,15 +315,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT V0.2S, V1.2S, #0.0 | FCMGE V0.2S, V1.2S, #0.0 | FCMEQ V0.2S, V1.2S, #0.0 | FCMLE V0.2S, V1.2S, #0.0 | FCMLT V0.2S, V1.2S, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(8)] float A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(RndCnt)] float A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x0EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetVector128(0, 0, A, A); @@ -339,15 +358,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT V0.4S, V1.4S, #0.0 | FCMGE V0.4S, V1.4S, #0.0 | FCMEQ V0.4S, V1.4S, #0.0 | FCMLE V0.4S, V1.4S, #0.0 | FCMLT V0.4S, V1.4S, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(8)] float A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(RndCnt)] float A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x4EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V1 = Sse.SetAllVector128(A); AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); @@ -379,6 +400,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs index 1e58a68a61..4efd8f31a2 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs @@ -22,6 +22,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E285800; // AESD V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH); Vector128 V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH); @@ -37,6 +38,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL)); Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH)); }); + CompareAgainstUnicorn(); } @@ -52,6 +54,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E284800; // AESE V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH); Vector128 V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH); @@ -67,6 +70,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL)); Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH)); }); + CompareAgainstUnicorn(); } @@ -80,6 +84,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E287800; // AESIMC V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V = MakeVectorE0E1(ValueL, ValueH); AThreadState ThreadState = SingleOpcode( @@ -100,6 +105,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH)); }); } + CompareAgainstUnicorn(); } @@ -113,6 +119,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E286800; // AESMC V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V = MakeVectorE0E1(ValueL, ValueH); AThreadState ThreadState = SingleOpcode( @@ -133,6 +140,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH)); }); } + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs index 7f5f05ee4f..fc089d3b59 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs @@ -24,6 +24,7 @@ namespace Ryujinx.Tests.Cpu public void Fcvtl_V_f16(ushort Value, uint Result) { uint Opcode = 0x0E217801; + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(Value)); AThreadState ThreadState = SingleOpcode(Opcode, V0: V0); @@ -35,6 +36,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V1), (byte)2), Is.EqualTo(Result)); Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V1), (byte)3), Is.EqualTo(Result)); }); + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index b7633e8be5..1cb11615c0 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -8,18 +8,10 @@ using System.Runtime.Intrinsics; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("SimdReg")/*, Ignore("Tested: second half of 2018.")*/] + [Category("SimdReg")] // Tested: second half of 2018. public sealed class CpuTestSimdReg : CpuTest { #if SimdReg - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } #region "ValueSource" private static ulong[] _1B1H1S1D_() @@ -98,23 +90,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE08400; // ADD D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Add_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -130,23 +112,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208400; // ADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Add_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -162,23 +134,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208400; // ADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Add_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -194,23 +156,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E204000; // ADDHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Addhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -226,23 +178,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E204000; // ADDHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Addhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -258,23 +200,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20BC00; // ADDP V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Addp_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -290,23 +222,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20BC00; // ADDP V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Addp_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -320,23 +242,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E201C00; // AND V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -350,23 +262,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E201C00; // AND V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -380,23 +282,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E601C00; // BIC V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -410,23 +302,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E601C00; // BIC V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -440,23 +322,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2EE01C00; // BIF V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -470,23 +342,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6EE01C00; // BIF V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -500,23 +362,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2EA01C00; // BIT V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -530,23 +382,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6EA01C00; // BIT V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -560,23 +402,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E601C00; // BSL V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -590,23 +422,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E601C00; // BSL V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -620,23 +442,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE08C00; // CMEQ D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmeq_Reg_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -652,23 +464,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208C00; // CMEQ V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmeq_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -684,23 +486,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208C00; // CMEQ V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmeq_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -714,23 +506,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE03C00; // CMGE D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmge_Reg_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -746,23 +528,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E203C00; // CMGE V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmge_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -778,23 +550,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E203C00; // CMGE V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmge_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -808,23 +570,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE03400; // CMGT D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmgt_Reg_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -840,23 +592,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E203400; // CMGT V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmgt_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -872,23 +614,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E203400; // CMGT V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmgt_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -902,23 +634,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE03400; // CMHI D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhi_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -934,23 +656,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E203400; // CMHI V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhi_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -966,23 +678,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E203400; // CMHI V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmhi_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -996,23 +698,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE03C00; // CMHS D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhs_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1028,23 +720,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E203C00; // CMHS V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhs_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1060,23 +742,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E203C00; // CMHS V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmhs_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1090,23 +762,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE08C00; // CMTST D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmtst_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1122,23 +784,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208C00; // CMTST V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmtst_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1154,23 +806,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208C00; // CMTST V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmtst_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1184,23 +826,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E201C00; // EOR V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Eor_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1214,23 +846,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E201C00; // EOR V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Eor_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1244,23 +866,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0EE01C00; // ORN V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1274,23 +886,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4EE01C00; // ORN V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1304,23 +906,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0EA01C00; // ORR V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1334,23 +926,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4EA01C00; // ORR V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1366,23 +948,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E204000; // RADDHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Raddhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1398,23 +970,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E204000; // RADDHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Raddhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1430,23 +992,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E206000; // RSUBHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Rsubhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1462,23 +1014,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E206000; // RSUBHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Rsubhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1494,23 +1036,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E207C00; // SABA V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Saba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1526,23 +1058,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E207C00; // SABA V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Saba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1558,23 +1080,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E205000; // SABAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Sabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1590,23 +1102,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E205000; // SABAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1622,23 +1124,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E207400; // SABD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1654,23 +1146,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E207400; // SABD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1686,23 +1168,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E207000; // SABDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Sabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1718,23 +1190,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E207000; // SABDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1750,23 +1212,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E200000; // SADDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Saddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SADDL{2} ., ., .")] @@ -1781,23 +1234,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E200000; // SADDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Saddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SADDW{2} ., ., .")] @@ -1812,23 +1256,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E201000; // SADDW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Saddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1844,23 +1278,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E201000; // SADDW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Saddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1874,31 +1298,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E004000; // SHA256H Q0, Q0, V0.4S Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); Vector128 V2 = MakeVectorE0E1(B0, B1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1)); - SimdFp.Sha256h_V(Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1912,31 +1318,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E005000; // SHA256H2 Q0, Q0, V0.4S Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); Vector128 V2 = MakeVectorE0E1(B0, B1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1)); - SimdFp.Sha256h2_V(Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1950,31 +1338,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E006000; // SHA256SU1 V0.4S, V0.4S, V0.4S Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); Vector128 V2 = MakeVectorE0E1(B0, B1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1)); - SimdFp.Sha256su1_V(Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - - Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1990,23 +1360,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E200400; // SHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SHADD ., ., .")] @@ -2021,23 +1382,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E200400; // SHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SHSUB ., ., .")] @@ -2052,23 +1404,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E202400; // SHSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SHSUB ., ., .")] @@ -2083,23 +1426,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E202400; // SHSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLAL{2} ., ., .")] @@ -2114,23 +1448,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208000; // SMLAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Smlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLAL{2} ., ., .")] @@ -2145,23 +1470,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208000; // SMLAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Smlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLSL{2} ., ., .")] @@ -2176,23 +1492,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20A000; // SMLSL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Smlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLSL{2} ., ., .")] @@ -2207,23 +1514,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20A000; // SMLSL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Smlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQADD , , ")] @@ -2235,30 +1533,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E200C00; // SQADD B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQADD ., ., .")] @@ -2270,30 +1555,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E200C00; // SQADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQADD ., ., .")] @@ -2305,30 +1577,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E200C00; // SQADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQDMULH , , ")] @@ -2340,30 +1599,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E20B400; // SQDMULH B0, B0, B0 (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQDMULH ., ., .")] @@ -2375,30 +1621,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E20B400; // SQDMULH V0.8B, V0.8B, V0.8B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQDMULH ., ., .")] @@ -2410,30 +1643,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <8H, 4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E20B400; // SQDMULH V0.16B, V0.16B, V0.16B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQRDMULH , , ")] @@ -2445,30 +1665,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E20B400; // SQRDMULH B0, B0, B0 (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqrdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQRDMULH ., ., .")] @@ -2480,30 +1687,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E20B400; // SQRDMULH V0.8B, V0.8B, V0.8B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQRDMULH ., ., .")] @@ -2515,30 +1709,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <8H, 4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E20B400; // SQRDMULH V0.16B, V0.16B, V0.16B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQSUB , , ")] @@ -2550,30 +1731,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E202C00; // SQSUB B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQSUB ., ., .")] @@ -2585,30 +1753,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E202C00; // SQSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQSUB ., ., .")] @@ -2620,30 +1775,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E202C00; // SQSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SRHADD ., ., .")] @@ -2658,23 +1800,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E201400; // SRHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SRHADD ., ., .")] @@ -2689,23 +1822,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E201400; // SRHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SSUBL{2} ., ., .")] @@ -2720,23 +1844,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E202000; // SSUBL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Ssubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SSUBL{2} ., ., .")] @@ -2751,23 +1866,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E202000; // SSUBL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Ssubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SSUBW{2} ., ., .")] @@ -2782,23 +1888,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E203000; // SSUBW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Ssubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2814,23 +1910,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E203000; // SSUBW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Ssubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2844,23 +1930,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE08400; // SUB D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2876,23 +1952,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208400; // SUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2908,23 +1974,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208400; // SUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2940,23 +1996,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E206000; // SUBHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Subhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2972,23 +2018,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E206000; // SUBHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Subhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3004,23 +2040,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E002800; // TRN1 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Trn1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3036,23 +2062,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E002800; // TRN1 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Trn1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3068,23 +2084,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E006800; // TRN2 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Trn2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3100,23 +2106,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E006800; // TRN2 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Trn2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3132,23 +2128,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E207C00; // UABA V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uaba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3164,23 +2150,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E207C00; // UABA V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uaba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3196,23 +2172,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E205000; // UABAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3228,23 +2194,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E205000; // UABAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3260,23 +2216,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E207400; // UABD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3292,23 +2238,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E207400; // UABD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3324,23 +2260,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E207000; // UABDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3356,23 +2282,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E207000; // UABDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3388,23 +2304,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E200000; // UADDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uaddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UADDL{2} ., ., .")] @@ -3419,23 +2326,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E200000; // UADDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uaddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UADDW{2} ., ., .")] @@ -3450,23 +2348,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E201000; // UADDW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uaddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3482,23 +2370,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E201000; // UADDW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uaddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3514,23 +2392,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E200400; // UHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UHADD ., ., .")] @@ -3545,23 +2414,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E200400; // UHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UHSUB ., ., .")] @@ -3576,23 +2436,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E202400; // UHSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UHSUB ., ., .")] @@ -3607,23 +2458,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E202400; // UHSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLAL{2} ., ., .")] @@ -3638,23 +2480,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208000; // UMLAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Umlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLAL{2} ., ., .")] @@ -3669,23 +2502,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208000; // UMLAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Umlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLSL{2} ., ., .")] @@ -3700,23 +2524,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E20A000; // UMLSL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Umlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLSL{2} ., ., .")] @@ -3731,23 +2546,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E20A000; // UMLSL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Umlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQADD , , ")] @@ -3759,30 +2565,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E200C00; // UQADD B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQADD ., ., .")] @@ -3794,30 +2587,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E200C00; // UQADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQADD ., ., .")] @@ -3829,30 +2609,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E200C00; // UQADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQSUB , , ")] @@ -3864,30 +2631,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E202C00; // UQSUB B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQSUB ., ., .")] @@ -3899,30 +2653,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E202C00; // UQSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQSUB ., ., .")] @@ -3934,30 +2675,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E202C00; // UQSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("URHADD ., ., .")] @@ -3972,23 +2700,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E201400; // URHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("URHADD ., ., .")] @@ -4003,23 +2722,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E201400; // URHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("USUBL{2} ., ., .")] @@ -4034,23 +2744,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E202000; // USUBL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Usubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("USUBL{2} ., ., .")] @@ -4065,23 +2766,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E202000; // USUBL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Usubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("USUBW{2} ., ., .")] @@ -4096,23 +2788,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E203000; // USUBW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Usubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4128,23 +2810,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E203000; // USUBW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Usubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4160,23 +2832,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E001800; // UZP1 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uzp1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4192,23 +2854,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E001800; // UZP1 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uzp1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4224,23 +2876,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E005800; // UZP2 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uzp2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4256,23 +2898,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E005800; // UZP2 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uzp2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4288,23 +2920,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E003800; // ZIP1 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Zip1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4320,23 +2942,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E003800; // ZIP1 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Zip1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4352,23 +2964,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E007800; // ZIP2 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Zip2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4384,23 +2986,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E007800; // ZIP2 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Zip2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } #endif